dpte_req_width    393 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int dpte_req_width = 0;
dpte_req_width    584 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	dpte_req_width = 1 << log2_dpte_req_width;
dpte_req_width    595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 										* dpte_req_width)
dpte_req_width    609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				dpte_req_width,
dpte_req_width    610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				1) + dpte_req_width;
dpte_req_width    611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_req_width    618 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 					+ dpte_req_width;
dpte_req_width    619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    393 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int dpte_req_width = 0;
dpte_req_width    584 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	dpte_req_width = 1 << log2_dpte_req_width;
dpte_req_width    595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 										* dpte_req_width)
dpte_req_width    609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				dpte_req_width,
dpte_req_width    610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				1) + dpte_req_width;
dpte_req_width    611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_req_width    618 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 					+ dpte_req_width;
dpte_req_width    619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    385 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int dpte_req_width = 0;
dpte_req_width    582 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	dpte_req_width = 1 << log2_dpte_req_width;
dpte_req_width    597 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 										* dpte_req_width)
dpte_req_width    612 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				dpte_req_width,
dpte_req_width    613 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				1) + dpte_req_width;
dpte_req_width    614 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    620 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_req_width    621 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 					+ dpte_req_width;
dpte_req_width    622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    405 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int dpte_req_width;
dpte_req_width    472 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	dpte_req_width = 0; /* 64b dpte req width in data element */
dpte_req_width    498 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	dpte_req_width = 1 << log2_dpte_req_width;
dpte_req_width    505 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
dpte_req_width    599 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int dpte_req_width;
dpte_req_width    793 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	dpte_req_width = 0; /* 64b dpte req width in data element */
dpte_req_width    825 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	dpte_req_width = 1 << log2_dpte_req_width;
dpte_req_width    832 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
dpte_req_width    848 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				dpte_req_width,
dpte_req_width    849 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				1) + dpte_req_width;
dpte_req_width    850 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_req_width    855 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_req_width    856 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 					+ dpte_req_width;
dpte_req_width    857 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;