dprefclk_khz      159 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
dprefclk_khz      136 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	clk_mgr->base.dprefclk_khz = 600000;
dprefclk_khz      143 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c 	clk_mgr->base.dprefclk_khz = 625000;
dprefclk_khz      266 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	clk_mgr->base.dprefclk_khz = 600000;
dprefclk_khz      121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 			clk_mgr->base.dprefclk_khz / 1000);
dprefclk_khz      447 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
dprefclk_khz      482 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
dprefclk_khz      328 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	s->dprefclk_khz = sb.dprefclk;
dprefclk_khz      544 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr->base.dprefclk_khz = 600000;
dprefclk_khz      556 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		clk_mgr->base.dprefclk_khz = s.dprefclk;
dprefclk_khz      558 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		if (clk_mgr->base.dprefclk_khz != 600000) {
dprefclk_khz      559 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			clk_mgr->base.dprefclk_khz = 600000;
dprefclk_khz      564 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		if (clk_mgr->base.dprefclk_khz == 0)
dprefclk_khz      565 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			clk_mgr->base.dprefclk_khz = 600000;
dprefclk_khz      116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 			clk_mgr->base.dprefclk_khz / 1000);
dprefclk_khz      178 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
dprefclk_khz      930 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	clk_mgr_dce->dprefclk_khz = 600000;
dprefclk_khz      951 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	clk_mgr_dce->dprefclk_khz = 625000;
dprefclk_khz      159 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	uint32_t dprefclk_khz;
dprefclk_khz      189 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes