dpps              527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
dpps              528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
dpps             1217 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.dpp = pool->dpps[i];
dpps             1219 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
dpps             1621 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.dpp = pool->dpps[i];
dpps             1623 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			if (pool->dpps[i])
dpps             1624 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
dpps             1891 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
dpps             1894 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (pool->dpps[tg_inst])
dpps             1895 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
dpps              258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dpp *dpp = pool->dpps[i];
dpps             1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dpp *dpp = dc->res_pool->dpps[i];
dpps              342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct dpp *dpp = pool->dpps[i];
dpps              910 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		if (pool->base.dpps[i] != NULL)
dpps              911 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			dcn10_dpp_destroy(&pool->base.dpps[i]);
dpps             1112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
dpps             1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
dpps             1470 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
dpps             1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		if (pool->base.dpps[j] == NULL) {
dpps             2039 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dpp *dpp = res_pool->dpps[i];
dpps             2059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct dpp *dpp = dc->res_pool->dpps[i];
dpps             1331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.dpps[i] != NULL)
dpps             1332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dcn20_dpp_destroy(&pool->base.dpps[i]);
dpps             1737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
dpps             1738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
dpps             1817 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
dpps             1818 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
dpps             2955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
dpps             2956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
dpps             3635 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
dpps             3636 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.dpps[i] == NULL) {
dpps              859 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.dpps[i] != NULL)
dpps              860 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			dcn20_dpp_destroy(&pool->base.dpps[i]);
dpps             1564 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
dpps             1565 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.dpps[i] == NULL) {
dpps              169 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dpp *dpps[MAX_PIPES];