dpp_inst          108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		int dpp_inst, dppclk_khz;
dpp_inst          113 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
dpp_inst          116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				clk_mgr->dccg, dpp_inst, dppclk_khz, false);
dpp_inst          282 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				int dpp_inst, dppclk_khz;
dpp_inst          287 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
dpp_inst          290 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
dpp_inst          299 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				int dpp_inst, dppclk_khz;
dpp_inst          304 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
dpp_inst          307 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
dpp_inst          498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		unsigned int dpp_inst,
dpp_inst          509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	switch (dpp_inst) {
dpp_inst           48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		int dpp_inst,
dpp_inst           69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst],
dpp_inst           76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
dpp_inst           80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
dpp_inst           85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
dpp_inst           91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				DPPCLK_DTO_ENABLE[dpp_inst], 1);
dpp_inst           94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				DPPCLK_DTO_ENABLE[dpp_inst], 0);
dpp_inst          100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
dpp_inst          327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		unsigned int dpp_inst,
dpp_inst          338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	switch (dpp_inst) {
dpp_inst           40 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 			int dpp_inst,
dpp_inst          302 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			unsigned int dpp_inst,