dpp_base 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c void dpp_read_state(struct dpp *dpp_base, dpp_base 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c void dpp_reset(struct dpp *dpp_base) dpp_base 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) dpp_base 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_power_on_regamma_lut(dpp_base, true); dpp_base 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); dpp_base 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_program_regamma_luta_settings(dpp_base, params); dpp_base 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_program_regamma_lutb_settings(dpp_base, params); dpp_base 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, dpp_base 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_set_degamma_format_float(dpp_base, is_float); dpp_base 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); dpp_base 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp1_program_input_csc(dpp_base, color_space, select, NULL); dpp_base 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 449 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 491 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dpp *dpp_base, dpp_base 507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 1370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_full_bypass(struct dpp *dpp_base); dpp_base 1434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1437 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_set_degamma_pwl(struct dpp *dpp_base, dpp_base 1441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp_read_state(struct dpp *dpp_base, dpp_base 1444 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp_reset(struct dpp *dpp_base); dpp_base 1447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1461 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1469 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h void dpp1_full_bypass(struct dpp *dpp_base); dpp_base 1499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 1504 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp *dpp_base, dpp_base 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, dpp_base 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, dpp_base 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 444 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 568 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 592 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 603 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base) dpp_base 605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 616 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_enable_cm_block(dpp_base); dpp_base 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 677 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_set_degamma_pwl(struct dpp *dpp_base, dpp_base 704 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_power_on_degamma_lut(dpp_base, true); dpp_base 705 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_enable_cm_block(dpp_base); dpp_base 706 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_degamma_ram_inuse(dpp_base, &is_ram_a); dpp_base 708 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_program_degamma_lutb_settings(dpp_base, params); dpp_base 710 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_program_degamma_luta_settings(dpp_base, params); dpp_base 712 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_program_degamma_lut(dpp_base, params->rgb_resulted, dpp_base 714 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_degamma_ram_select(dpp_base, !is_ram_a); dpp_base 717 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c void dpp1_full_bypass(struct dpp *dpp_base) dpp_base 719 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base, dpp_base 748 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 775 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 779 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 784 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_enable_cm_block(dpp_base); dpp_base 786 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_ingamma_ram_inuse(dpp_base, &rama_occupied); dpp_base 824 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dpp *dpp_base, dpp_base 827 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp_base 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { dpp_base 527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp_base 531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); dpp_base 666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dpp *dpp_base, dpp_base 670 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_base 672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); dpp_base 1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp_base 1396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dpp_base == NULL) dpp_base 1403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c !dpp_base->ctx->dc->debug.always_use_regamma dpp_base 1406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); dpp_base 1409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); dpp_base 1413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); dpp_base 1416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); dpp_base 1419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); dpp_base 1427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); dpp_base 1430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dpp_base->degamma_params); dpp_base 1431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, dpp_base 1432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &dpp_base->degamma_params); dpp_base 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c void dpp20_read_state(struct dpp *dpp_base, dpp_base 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); dpp_base 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp1_program_input_csc(dpp_base, color_space, select, NULL); dpp_base 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp2_power_on_obuf(dpp_base, true); dpp_base 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dpp *dpp_base, dpp_base 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h void dpp20_read_state(struct dpp *dpp_base, dpp_base 649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, const struct pwl_params *params); dpp_base 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 682 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 707 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp *dpp_base, dpp_base 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base) dpp_base 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c if (dpp_base->ctx->dc->debug.cm_in_bypass) dpp_base 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp1_power_on_degamma_lut(dpp_base, true); dpp_base 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp2_enable_cm_block(dpp_base); dpp_base 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp2_degamma_ram_inuse(dpp_base, &is_ram_a); dpp_base 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp1_program_degamma_lutb_settings(dpp_base, params); dpp_base 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp1_program_degamma_luta_settings(dpp_base, params); dpp_base 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); dpp_base 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp1_degamma_ram_select(dpp_base, !is_ram_a); dpp_base 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp2_enable_cm_block(dpp_base); dpp_base 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base) dpp_base 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, const struct pwl_params *params) dpp_base 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c current_mode = dpp20_get_blndgam_current(dpp_base); dpp_base 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_power_on_blnd_lut(dpp_base, true); dpp_base 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); dpp_base 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_program_blnd_luta_settings(dpp_base, params); dpp_base 338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_program_blnd_lutb_settings(dpp_base, params); dpp_base 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp_base, params->rgb_resulted, params->hw_points_num); dpp_base 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base) dpp_base 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c current_mode = dpp20_get_shaper_current(dpp_base); dpp_base 744 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); dpp_base 747 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_program_shaper_luta_settings(dpp_base, params); dpp_base 749 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_program_shaper_lutb_settings(dpp_base, params); dpp_base 752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp_base, params->rgb_resulted, params->hw_points_num); dpp_base 761 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 767 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 828 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 832 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 843 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 877 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 882 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 898 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 901 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 909 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 923 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); dpp_base 926 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); dpp_base 955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_select_3dlut_ram(dpp_base, mode, dpp_base 957 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_select_3dlut_ram_mask(dpp_base, 0x1); dpp_base 959 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram12(dpp_base, lut0, lut_size0); dpp_base 961 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram10(dpp_base, lut0, lut_size0); dpp_base 963 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_select_3dlut_ram_mask(dpp_base, 0x2); dpp_base 965 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram12(dpp_base, lut1, lut_size); dpp_base 967 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram10(dpp_base, lut1, lut_size); dpp_base 969 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_select_3dlut_ram_mask(dpp_base, 0x4); dpp_base 971 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram12(dpp_base, lut2, lut_size); dpp_base 973 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram10(dpp_base, lut2, lut_size); dpp_base 975 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_select_3dlut_ram_mask(dpp_base, 0x8); dpp_base 977 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram12(dpp_base, lut3, lut_size); dpp_base 979 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set3dlut_ram10(dpp_base, lut3, lut_size); dpp_base 982 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp20_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, dpp_base 989 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dpp *dpp_base, dpp_base 992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp_base 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp_base 703 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dpp_base->regamma_params, false); dpp_base 704 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c blend_lut = &dpp_base->regamma_params; dpp_base 707 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); dpp_base 715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp_base 725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dpp_base->shaper_params, true); dpp_base 726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c shaper_lut = &dpp_base->shaper_params; dpp_base 730 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); dpp_base 733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c result = dpp_base->funcs->dpp_program_3dlut(dpp_base, dpp_base 736 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); dpp_base 741 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, dpp_base 744 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000); dpp_base 752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct dpp *dpp_base = pipe_ctx->plane_res.dpp; dpp_base 757 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (dpp_base == NULL || plane_state == NULL) dpp_base 768 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 778 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, dpp_base 782 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dpp_base->degamma_params); dpp_base 783 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, dpp_base 784 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &dpp_base->degamma_params); dpp_base 794 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 798 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 802 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 811 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 819 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dpp_base->funcs->dpp_set_degamma(dpp_base, dpp_base 111 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_program_cm_dealpha)(struct dpp *dpp_base, dpp_base 115 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 178 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 182 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 185 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_program_degamma_pwl)(struct dpp *dpp_base, dpp_base 189 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 200 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h void (*dpp_full_bypass)(struct dpp *dpp_base); dpp_base 203 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 207 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 215 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 219 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 223 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base, dpp_base 238 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct dpp *dpp_base,