dpm_level_enable_mask 2605 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { dpm_level_enable_mask 2607 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; dpm_level_enable_mask 2618 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 2620 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; dpm_level_enable_mask 2632 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { dpm_level_enable_mask 2634 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; dpm_level_enable_mask 2657 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) dpm_level_enable_mask 2660 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask); dpm_level_enable_mask 2664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) dpm_level_enable_mask 2667 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 2695 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 2697 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask); dpm_level_enable_mask 2705 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { dpm_level_enable_mask 2707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 2715 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { dpm_level_enable_mask 2717 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask); dpm_level_enable_mask 3863 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 3865 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 3867 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 4412 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); dpm_level_enable_mask 4418 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); dpm_level_enable_mask 4422 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; dpm_level_enable_mask 4988 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 4990 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; dpm_level_enable_mask 4997 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); dpm_level_enable_mask 294 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; dpm_level_enable_mask 369 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; dpm_level_enable_mask 372 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; dpm_level_enable_mask 496 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; dpm_level_enable_mask 500 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 1015 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 1338 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); dpm_level_enable_mask 2876 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; dpm_level_enable_mask 2880 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 2885 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.uvd_dpm_enable_mask); dpm_level_enable_mask 2907 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; dpm_level_enable_mask 2911 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 2916 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.vce_dpm_enable_mask); dpm_level_enable_mask 851 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 1047 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 1059 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 1060 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1064 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 1065 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1070 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1262 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 789 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 1002 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 1005 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1010 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1016 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1383 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); dpm_level_enable_mask 791 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 1020 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 1033 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 1034 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1038 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 1039 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1044 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1164 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 532 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 732 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 745 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) dpm_level_enable_mask 748 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 749 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 754 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 755 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 761 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1131 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); dpm_level_enable_mask 593 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c data->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 907 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 912 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; dpm_level_enable_mask 923 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 924 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 928 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && dpm_level_enable_mask 929 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 934 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & dpm_level_enable_mask 1065 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 1070 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; dpm_level_enable_mask 2644 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 3305 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 3359 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 3823 drivers/gpu/drm/radeon/ci_dpm.c if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 3826 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask); dpm_level_enable_mask 3833 drivers/gpu/drm/radeon/ci_dpm.c if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { dpm_level_enable_mask 3836 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 3843 drivers/gpu/drm/radeon/ci_dpm.c if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { dpm_level_enable_mask 3846 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask); dpm_level_enable_mask 3943 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; dpm_level_enable_mask 3947 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 3956 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.uvd_dpm_enable_mask); dpm_level_enable_mask 3960 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; dpm_level_enable_mask 3963 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 3968 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; dpm_level_enable_mask 3971 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 3992 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; dpm_level_enable_mask 3995 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 4004 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.vce_dpm_enable_mask); dpm_level_enable_mask 4025 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; dpm_level_enable_mask 4028 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 4037 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.samu_dpm_enable_mask); dpm_level_enable_mask 4056 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; dpm_level_enable_mask 4059 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; dpm_level_enable_mask 4068 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.acp_dpm_enable_mask); dpm_level_enable_mask 4178 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask = dpm_level_enable_mask 4180 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask = dpm_level_enable_mask 4183 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask; dpm_level_enable_mask 4185 drivers/gpu/drm/radeon/ci_dpm.c if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) dpm_level_enable_mask 4186 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; dpm_level_enable_mask 4188 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask = dpm_level_enable_mask 4215 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { dpm_level_enable_mask 4217 drivers/gpu/drm/radeon/ci_dpm.c tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; dpm_level_enable_mask 4234 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 4236 drivers/gpu/drm/radeon/ci_dpm.c tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; dpm_level_enable_mask 4253 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { dpm_level_enable_mask 4255 drivers/gpu/drm/radeon/ci_dpm.c tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; dpm_level_enable_mask 4273 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { dpm_level_enable_mask 4275 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.sclk_dpm_enable_mask); dpm_level_enable_mask 4288 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { dpm_level_enable_mask 4290 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.mclk_dpm_enable_mask); dpm_level_enable_mask 4303 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { dpm_level_enable_mask 4305 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_level_enable_mask.pcie_dpm_enable_mask); dpm_level_enable_mask 238 drivers/gpu/drm/radeon/ci_dpm.h struct ci_dpm_level_enable_mask dpm_level_enable_mask;