dpll_reg          219 drivers/gpu/drm/gma500/cdv_intel_display.c 	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
dpll_reg          226 drivers/gpu/drm/gma500/cdv_intel_display.c 	REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
dpll_reg          629 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	pkg_sender->dpll_reg = map->dpll;
dpll_reg           46 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h 	u32 dpll_reg;
dpll_reg         1593 drivers/gpu/drm/i915/display/intel_display.c 	i915_reg_t dpll_reg;
dpll_reg         1598 drivers/gpu/drm/i915/display/intel_display.c 		dpll_reg = DPLL(0);
dpll_reg         1602 drivers/gpu/drm/i915/display/intel_display.c 		dpll_reg = DPLL(0);
dpll_reg         1607 drivers/gpu/drm/i915/display/intel_display.c 		dpll_reg = DPIO_PHY_STATUS;
dpll_reg         1613 drivers/gpu/drm/i915/display/intel_display.c 	if (intel_de_wait_for_register(dev_priv, dpll_reg,
dpll_reg         1617 drivers/gpu/drm/i915/display/intel_display.c 		     I915_READ(dpll_reg) & port_mask, expected_mask);
dpll_reg         1283 drivers/video/fbdev/intelfb/intelfbhw.c 	u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
dpll_reg         1314 drivers/video/fbdev/intelfb/intelfbhw.c 		dpll_reg = DPLL_B;
dpll_reg         1338 drivers/video/fbdev/intelfb/intelfbhw.c 		dpll_reg = DPLL_A;
dpll_reg         1398 drivers/video/fbdev/intelfb/intelfbhw.c 	tmp = INREG(dpll_reg);
dpll_reg         1400 drivers/video/fbdev/intelfb/intelfbhw.c 	OUTREG(dpll_reg, tmp);
dpll_reg         1407 drivers/video/fbdev/intelfb/intelfbhw.c 	OUTREG(dpll_reg, *dpll);