dpll_md           523 drivers/gpu/drm/gma500/cdv_device.c 		.dpll_md = DPLL_A_MD,
dpll_md           548 drivers/gpu/drm/gma500/cdv_device.c 		.dpll_md = DPLL_B_MD,
dpll_md            93 drivers/gpu/drm/gma500/cdv_intel_crt.c 	u32 adpa, dpll_md;
dpll_md           108 drivers/gpu/drm/gma500/cdv_intel_crt.c 		dpll_md = REG_READ(dpll_md_reg);
dpll_md           110 drivers/gpu/drm/gma500/cdv_intel_crt.c 			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
dpll_md           784 drivers/gpu/drm/gma500/cdv_intel_display.c 		REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
dpll_md           271 drivers/gpu/drm/gma500/psb_drv.h 	u32	dpll_md;
dpll_md           305 drivers/gpu/drm/gma500/psb_drv.h 	u32	dpll_md;
dpll_md          1403 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
dpll_md          1460 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
dpll_md          1462 drivers/gpu/drm/i915/display/intel_display.c 		dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
dpll_md          1470 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
dpll_md          1511 drivers/gpu/drm/i915/display/intel_display.c 			   crtc_state->dpll_hw_state.dpll_md);
dpll_md          7717 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->dpll_hw_state.dpll_md =
dpll_md          7733 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->dpll_hw_state.dpll_md =
dpll_md          8064 drivers/gpu/drm/i915/display/intel_display.c 		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
dpll_md          8066 drivers/gpu/drm/i915/display/intel_display.c 		crtc_state->dpll_hw_state.dpll_md = dpll_md;
dpll_md          8837 drivers/gpu/drm/i915/display/intel_display.c 		pipe_config->dpll_hw_state.dpll_md = tmp;
dpll_md          12796 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
dpll_md           489 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->dpll_md,
dpll_md          3652 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			      hw_state->dpll_md,
dpll_md           171 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 dpll_md;
dpll_md          2841 drivers/gpu/drm/i915/i915_debugfs.c 			   pll->state.hw_state.dpll_md);