dpll_hw_state 1250 drivers/gpu/drm/i915/display/icl_dsi.c cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); dpll_hw_state 1489 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; dpll_hw_state 1515 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; dpll_hw_state 1563 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; dpll_hw_state 1673 drivers/gpu/drm/i915/display/intel_ddi.c bxt_calc_pll_link(&pipe_config->dpll_hw_state); dpll_hw_state 1381 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); dpll_hw_state 1400 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) dpll_hw_state 1403 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); dpll_hw_state 1431 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); dpll_hw_state 1449 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) dpll_hw_state 1460 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); dpll_hw_state 1462 drivers/gpu/drm/i915/display/intel_display.c dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; dpll_hw_state 1470 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); dpll_hw_state 1488 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = crtc_state->dpll_hw_state.dpll; dpll_hw_state 1511 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll_md); dpll_hw_state 6913 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0); dpll_hw_state 6914 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1); dpll_hw_state 7580 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp0 = fp; dpll_hw_state 7584 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp2; dpll_hw_state 7586 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp; dpll_hw_state 7707 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | dpll_hw_state 7710 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; dpll_hw_state 7714 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | dpll_hw_state 7717 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = dpll_hw_state 7724 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | dpll_hw_state 7727 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; dpll_hw_state 7731 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; dpll_hw_state 7733 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = dpll_hw_state 7749 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & dpll_hw_state 7753 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll_hw_state 7851 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); dpll_hw_state 7854 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll_hw_state 8061 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll_hw_state 8066 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll_md = dpll_md; dpll_hw_state 8117 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll_hw_state 8346 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8347 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8381 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8382 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8424 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8425 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8458 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8459 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8490 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8491 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8511 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 8512 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 8572 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll_hw_state 8683 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) dpll_hw_state 8837 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = tmp; dpll_hw_state 8850 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); dpll_hw_state 8852 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); dpll_hw_state 8853 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); dpll_hw_state 8856 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | dpll_hw_state 9628 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; dpll_hw_state 9629 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp0 = fp; dpll_hw_state 9630 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp2; dpll_hw_state 9642 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 9643 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 10025 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dpll_hw_state)); dpll_hw_state 10027 drivers/gpu/drm/i915/display/intel_display.c tmp = pipe_config->dpll_hw_state.dpll; dpll_hw_state 10380 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dpll_hw_state)); dpll_hw_state 11271 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; dpll_hw_state 11290 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; dpll_hw_state 11297 drivers/gpu/drm/i915/display/intel_display.c fp = pipe_config->dpll_hw_state.fp0; dpll_hw_state 11299 drivers/gpu/drm/i915/display/intel_display.c fp = pipe_config->dpll_hw_state.fp1; dpll_hw_state 12160 drivers/gpu/drm/i915/display/intel_display.c intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); dpll_hw_state 12256 drivers/gpu/drm/i915/display/intel_display.c saved_state->dpll_hw_state = crtc_state->dpll_hw_state; dpll_hw_state 12795 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.dpll); dpll_hw_state 12796 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); dpll_hw_state 12797 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.fp0); dpll_hw_state 12798 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.fp1); dpll_hw_state 12799 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); dpll_hw_state 12800 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.spll); dpll_hw_state 12801 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); dpll_hw_state 12802 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); dpll_hw_state 12803 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); dpll_hw_state 12804 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); dpll_hw_state 12805 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); dpll_hw_state 12806 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); dpll_hw_state 12807 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll0); dpll_hw_state 12808 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll1); dpll_hw_state 12809 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll2); dpll_hw_state 12810 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll3); dpll_hw_state 12811 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll6); dpll_hw_state 12812 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll8); dpll_hw_state 12813 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll9); dpll_hw_state 12814 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll10); dpll_hw_state 12815 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); dpll_hw_state 12816 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); dpll_hw_state 12817 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); dpll_hw_state 12818 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); dpll_hw_state 12819 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); dpll_hw_state 12820 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); dpll_hw_state 12821 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); dpll_hw_state 12822 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); dpll_hw_state 12823 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); dpll_hw_state 12824 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); dpll_hw_state 12825 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); dpll_hw_state 13173 drivers/gpu/drm/i915/display/intel_display.c struct intel_dpll_hw_state dpll_hw_state; dpll_hw_state 13177 drivers/gpu/drm/i915/display/intel_display.c memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); dpll_hw_state 13181 drivers/gpu/drm/i915/display/intel_display.c active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); dpll_hw_state 13217 drivers/gpu/drm/i915/display/intel_display.c &dpll_hw_state, dpll_hw_state 13218 drivers/gpu/drm/i915/display/intel_display.c sizeof(dpll_hw_state)), dpll_hw_state 843 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_dpll_hw_state dpll_hw_state; dpll_hw_state 466 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); dpll_hw_state 828 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.wrpll = val; dpll_hw_state 831 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 879 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 880 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 890 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.spll = dpll_hw_state 894 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 904 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); dpll_hw_state 1388 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 1389 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 1391 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; dpll_hw_state 1392 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; dpll_hw_state 1393 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; dpll_hw_state 1429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 1430 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 1432 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; dpll_hw_state 1464 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 1469 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 1476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); dpll_hw_state 1800 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; dpll_hw_state 1806 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(dpll_hw_state, 0, sizeof(*dpll_hw_state)); dpll_hw_state 1840 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); dpll_hw_state 1841 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll0 = clk_div->m2_int; dpll_hw_state 1842 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); dpll_hw_state 1843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll2 = clk_div->m2_frac; dpll_hw_state 1846 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; dpll_hw_state 1848 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef); dpll_hw_state 1849 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl); dpll_hw_state 1851 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll8 = targ_cnt; dpll_hw_state 1853 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; dpll_hw_state 1855 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll10 = dpll_hw_state 1859 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE; dpll_hw_state 1861 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; dpll_hw_state 1912 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); dpll_hw_state 2337 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 2338 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 2340 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; dpll_hw_state 2341 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; dpll_hw_state 2382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, dpll_hw_state 2383 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); dpll_hw_state 2385 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; dpll_hw_state 2418 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, dpll_hw_state 2427 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); dpll_hw_state 2877 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state = port_dpll->hw_state;