dpio_val         7846 drivers/gpu/drm/i915/display/intel_display.c 	u32 dpio_val;
dpio_val         7864 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val = 0;
dpio_val         7888 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val         7889 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
dpio_val         7890 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
dpio_val         7892 drivers/gpu/drm/i915/display/intel_display.c 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
dpio_val         7893 drivers/gpu/drm/i915/display/intel_display.c 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
dpio_val         7896 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
dpio_val         7897 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
dpio_val         7899 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
dpio_val         7901 drivers/gpu/drm/i915/display/intel_display.c 		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
dpio_val         7902 drivers/gpu/drm/i915/display/intel_display.c 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
dpio_val         7929 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
dpio_val         7930 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
dpio_val         7931 drivers/gpu/drm/i915/display/intel_display.c 	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
dpio_val         7932 drivers/gpu/drm/i915/display/intel_display.c 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);