dpfc_ctl          171 drivers/gpu/drm/i915/display/intel_fbc.c 	u32 dpfc_ctl;
dpfc_ctl          173 drivers/gpu/drm/i915/display/intel_fbc.c 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
dpfc_ctl          175 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
dpfc_ctl          177 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
dpfc_ctl          180 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
dpfc_ctl          187 drivers/gpu/drm/i915/display/intel_fbc.c 	I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
dpfc_ctl          192 drivers/gpu/drm/i915/display/intel_fbc.c 	u32 dpfc_ctl;
dpfc_ctl          195 drivers/gpu/drm/i915/display/intel_fbc.c 	dpfc_ctl = I915_READ(DPFC_CONTROL);
dpfc_ctl          196 drivers/gpu/drm/i915/display/intel_fbc.c 	if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl          197 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl &= ~DPFC_CTL_EN;
dpfc_ctl          198 drivers/gpu/drm/i915/display/intel_fbc.c 		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
dpfc_ctl          217 drivers/gpu/drm/i915/display/intel_fbc.c 	u32 dpfc_ctl;
dpfc_ctl          220 drivers/gpu/drm/i915/display/intel_fbc.c 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
dpfc_ctl          227 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
dpfc_ctl          230 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
dpfc_ctl          233 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
dpfc_ctl          238 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_FENCE_EN;
dpfc_ctl          240 drivers/gpu/drm/i915/display/intel_fbc.c 			dpfc_ctl |= params->vma->fence->id;
dpfc_ctl          259 drivers/gpu/drm/i915/display/intel_fbc.c 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
dpfc_ctl          266 drivers/gpu/drm/i915/display/intel_fbc.c 	u32 dpfc_ctl;
dpfc_ctl          269 drivers/gpu/drm/i915/display/intel_fbc.c 	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
dpfc_ctl          270 drivers/gpu/drm/i915/display/intel_fbc.c 	if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl          271 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl &= ~DPFC_CTL_EN;
dpfc_ctl          272 drivers/gpu/drm/i915/display/intel_fbc.c 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
dpfc_ctl          284 drivers/gpu/drm/i915/display/intel_fbc.c 	u32 dpfc_ctl;
dpfc_ctl          300 drivers/gpu/drm/i915/display/intel_fbc.c 	dpfc_ctl = 0;
dpfc_ctl          302 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
dpfc_ctl          310 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
dpfc_ctl          313 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
dpfc_ctl          316 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
dpfc_ctl          321 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
dpfc_ctl          332 drivers/gpu/drm/i915/display/intel_fbc.c 		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
dpfc_ctl          350 drivers/gpu/drm/i915/display/intel_fbc.c 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);