dpcd 471 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 256 drivers/gpu/drm/amd/amdgpu/atombios_dp.c const u8 dpcd[DP_DPCD_SIZE], dpcd 263 drivers/gpu/drm/amd/amdgpu/atombios_dp.c unsigned max_link_rate = drm_dp_max_link_rate(dpcd); dpcd 264 drivers/gpu/drm/amd/amdgpu/atombios_dp.c unsigned max_lane_num = drm_dp_max_lane_count(dpcd); dpcd 325 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) dpcd 346 drivers/gpu/drm/amd/amdgpu/atombios_dp.c memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); dpcd 348 drivers/gpu/drm/amd/amdgpu/atombios_dp.c DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), dpcd 349 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dig_connector->dpcd); dpcd 356 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dig_connector->dpcd[0] = 0; dpcd 411 drivers/gpu/drm/amd/amdgpu/atombios_dp.c ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, dpcd 434 drivers/gpu/drm/amd/amdgpu/atombios_dp.c ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, dpcd 471 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if (dig_connector->dpcd[0] >= 0x11) { dpcd 485 drivers/gpu/drm/amd/amdgpu/atombios_dp.c u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 539 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if (dp_info->dpcd[3] & 0x1) dpcd 551 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) dpcd 606 drivers/gpu/drm/amd/amdgpu/atombios_dp.c drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); dpcd 671 drivers/gpu/drm/amd/amdgpu/atombios_dp.c drm_dp_link_train_channel_eq_delay(dp_info->dpcd); dpcd 745 drivers/gpu/drm/amd/amdgpu/atombios_dp.c memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); dpcd 77 drivers/gpu/drm/bridge/analogix-anx78xx.c u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 783 drivers/gpu/drm/bridge/analogix-anx78xx.c &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); dpcd 815 drivers/gpu/drm/bridge/analogix-anx78xx.c if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { dpcd 834 drivers/gpu/drm/bridge/analogix-anx78xx.c if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) dpcd 123 drivers/gpu/drm/drm_dp_helper.c void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { dpcd 124 drivers/gpu/drm/drm_dp_helper.c int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & dpcd 131 drivers/gpu/drm/drm_dp_helper.c if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) dpcd 138 drivers/gpu/drm/drm_dp_helper.c void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { dpcd 139 drivers/gpu/drm/drm_dp_helper.c int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & dpcd 477 drivers/gpu/drm/drm_dp_helper.c int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 481 drivers/gpu/drm/drm_dp_helper.c bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & dpcd 508 drivers/gpu/drm/drm_dp_helper.c int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 512 drivers/gpu/drm/drm_dp_helper.c bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & dpcd 565 drivers/gpu/drm/drm_dp_helper.c const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 568 drivers/gpu/drm/drm_dp_helper.c bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & dpcd 576 drivers/gpu/drm/drm_dp_helper.c bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & dpcd 625 drivers/gpu/drm/drm_dp_helper.c clk = drm_dp_downstream_max_clock(dpcd, port_cap); dpcd 634 drivers/gpu/drm/drm_dp_helper.c bpc = drm_dp_downstream_max_bpc(dpcd, port_cap); dpcd 2710 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); dpcd 2716 drivers/gpu/drm/drm_dp_mst_topology.c if (!drm_dp_get_vc_payload_bw(mgr->dpcd[1], dpcd 2717 drivers/gpu/drm/drm_dp_mst_topology.c mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, dpcd 2815 drivers/gpu/drm/drm_dp_mst_topology.c sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); dpcd 266 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t dpcd[4]; dpcd 329 drivers/gpu/drm/gma500/cdv_intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { dpcd 330 drivers/gpu/drm/gma500/cdv_intel_dp.c max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; dpcd 345 drivers/gpu/drm/gma500/cdv_intel_dp.c int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; dpcd 1079 drivers/gpu/drm/gma500/cdv_intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && dpcd 1080 drivers/gpu/drm/gma500/cdv_intel_dp.c (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { dpcd 1115 drivers/gpu/drm/gma500/cdv_intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) dpcd 1709 drivers/gpu/drm/gma500/cdv_intel_dp.c if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, dpcd 1710 drivers/gpu/drm/gma500/cdv_intel_dp.c sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) dpcd 1712 drivers/gpu/drm/gma500/cdv_intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] != 0) dpcd 1717 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->dpcd[0], intel_dp->dpcd[1], dpcd 1718 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->dpcd[2], intel_dp->dpcd[3]); dpcd 2120 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->dpcd, dpcd 2121 drivers/gpu/drm/gma500/cdv_intel_dp.c sizeof(intel_dp->dpcd)); dpcd 2131 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->dpcd[0], intel_dp->dpcd[1], dpcd 2132 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->dpcd[2], intel_dp->dpcd[3]); dpcd 3792 drivers/gpu/drm/i915/display/intel_ddi.c if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dpcd 1157 drivers/gpu/drm/i915/display/intel_display_types.h u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 177 drivers/gpu/drm/i915/display/intel_dp.c max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); dpcd 221 drivers/gpu/drm/i915/display/intel_dp.c int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); dpcd 265 drivers/gpu/drm/i915/display/intel_dp.c ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, dpcd 1875 drivers/gpu/drm/i915/display/intel_dp.c bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); dpcd 2404 drivers/gpu/drm/i915/display/intel_dp.c if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dpcd 2414 drivers/gpu/drm/i915/display/intel_dp.c if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dpcd 2429 drivers/gpu/drm/i915/display/intel_dp.c if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dpcd 3015 drivers/gpu/drm/i915/display/intel_dp.c return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && dpcd 3016 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && dpcd 3042 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) dpcd 3311 drivers/gpu/drm/i915/display/intel_dp.c u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); dpcd 4145 drivers/gpu/drm/i915/display/intel_dp.c if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] & dpcd 4155 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { dpcd 4160 drivers/gpu/drm/i915/display/intel_dp.c if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) dpcd 4164 drivers/gpu/drm/i915/display/intel_dp.c (int)sizeof(intel_dp->dpcd), intel_dp->dpcd); dpcd 4166 drivers/gpu/drm/i915/display/intel_dp.c memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)); dpcd 4172 drivers/gpu/drm/i915/display/intel_dp.c if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, dpcd 4173 drivers/gpu/drm/i915/display/intel_dp.c sizeof(intel_dp->dpcd)) < 0) dpcd 4178 drivers/gpu/drm/i915/display/intel_dp.c DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); dpcd 4180 drivers/gpu/drm/i915/display/intel_dp.c return intel_dp->dpcd[DP_DPCD_REV] != 0; dpcd 4205 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || dpcd 4234 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); dpcd 4240 drivers/gpu/drm/i915/display/intel_dp.c drm_dp_is_branch(intel_dp->dpcd)); dpcd 4319 drivers/gpu/drm/i915/display/intel_dp.c drm_dp_is_branch(intel_dp->dpcd)); dpcd 4356 drivers/gpu/drm/i915/display/intel_dp.c if (!drm_dp_is_branch(intel_dp->dpcd)) dpcd 4359 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) dpcd 4375 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) dpcd 4912 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) dpcd 4995 drivers/gpu/drm/i915/display/intel_dp.c u8 *dpcd = intel_dp->dpcd; dpcd 5008 drivers/gpu/drm/i915/display/intel_dp.c if (!drm_dp_is_branch(dpcd)) dpcd 5012 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && dpcd 5027 drivers/gpu/drm/i915/display/intel_dp.c if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { dpcd 5033 drivers/gpu/drm/i915/display/intel_dp.c type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & dpcd 153 drivers/gpu/drm/i915/display/intel_dp_link_training.c if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dpcd 184 drivers/gpu/drm/i915/display/intel_dp_link_training.c if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) dpcd 193 drivers/gpu/drm/i915/display/intel_dp_link_training.c drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); dpcd 254 drivers/gpu/drm/i915/display/intel_dp_link_training.c sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); dpcd 269 drivers/gpu/drm/i915/display/intel_dp_link_training.c sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); dpcd 304 drivers/gpu/drm/i915/display/intel_dp_link_training.c drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); dpcd 79 drivers/gpu/drm/i915/display/intel_lspcon.c if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { dpcd 457 drivers/gpu/drm/i915/display/intel_psr.c drm_dp_tps3_supported(intel_dp->dpcd)) dpcd 354 drivers/gpu/drm/i915/gvt/display.c kfree(port->dpcd); dpcd 355 drivers/gpu/drm/i915/gvt/display.c port->dpcd = NULL; dpcd 370 drivers/gpu/drm/i915/gvt/display.c port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); dpcd 371 drivers/gpu/drm/i915/gvt/display.c if (!port->dpcd) { dpcd 380 drivers/gpu/drm/i915/gvt/display.c memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); dpcd 381 drivers/gpu/drm/i915/gvt/display.c port->dpcd->data_valid = true; dpcd 382 drivers/gpu/drm/i915/gvt/display.c port->dpcd->data[DPCD_SINK_COUNT] = 0x1; dpcd 159 drivers/gpu/drm/i915/gvt/display.h struct intel_vgpu_dpcd_data *dpcd; dpcd 862 drivers/gpu/drm/i915/gvt/handlers.c static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, dpcd 868 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; dpcd 870 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; dpcd 875 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; dpcd 876 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; dpcd 878 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; dpcd 879 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; dpcd 881 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= dpcd 887 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; dpcd 907 drivers/gpu/drm/i915/gvt/handlers.c struct intel_vgpu_dpcd_data *dpcd = NULL; dpcd 936 drivers/gpu/drm/i915/gvt/handlers.c dpcd = port->dpcd; dpcd 985 drivers/gpu/drm/i915/gvt/handlers.c if (dpcd && dpcd->data_valid) { dpcd 989 drivers/gpu/drm/i915/gvt/handlers.c dpcd->data[p] = buf[t]; dpcd 992 drivers/gpu/drm/i915/gvt/handlers.c dp_aux_ch_ctl_link_training(dpcd, dpcd 1000 drivers/gpu/drm/i915/gvt/handlers.c dpcd && dpcd->data_valid); dpcd 1043 drivers/gpu/drm/i915/gvt/handlers.c if (dpcd && dpcd->data_valid) { dpcd 1047 drivers/gpu/drm/i915/gvt/handlers.c t = dpcd->data[addr + i - 1]; dpcd 1059 drivers/gpu/drm/i915/gvt/handlers.c dpcd && dpcd->data_valid); dpcd 2512 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); dpcd 2517 drivers/gpu/drm/i915/i915_debugfs.c drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, dpcd 96 drivers/gpu/drm/msm/edp/edp_ctrl.c u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 612 drivers/gpu/drm/msm/edp/edp_ctrl.c drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); dpcd 669 drivers/gpu/drm/msm/edp/edp_ctrl.c drm_dp_link_train_channel_eq_delay(ctrl->dpcd); dpcd 747 drivers/gpu/drm/msm/edp/edp_ctrl.c drm_dp_link_train_channel_eq_delay(ctrl->dpcd); dpcd 1188 drivers/gpu/drm/msm/edp/edp_ctrl.c if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, dpcd 1191 drivers/gpu/drm/msm/edp/edp_ctrl.c memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); dpcd 1235 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) dpcd 1252 drivers/gpu/drm/nouveau/dispnv50/disp.c if (dpcd >= 0x12) { dpcd 1274 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) dpcd 1297 drivers/gpu/drm/nouveau/dispnv50/disp.c } else if (dpcd[0] >= 0x12) { dpcd 1298 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); dpcd 1302 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!(dpcd[1] & DP_MST_CAP)) dpcd 1303 drivers/gpu/drm/nouveau/dispnv50/disp.c dpcd[0] = 0x11; dpcd 1313 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_mstm_enable(mstm, dpcd[0], new_state); dpcd 1321 drivers/gpu/drm/nouveau/dispnv50/disp.c return nv50_mstm_enable(mstm, dpcd[0], 0); dpcd 1371 drivers/gpu/drm/nouveau/dispnv50/disp.c u8 dpcd; dpcd 1379 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); dpcd 1380 drivers/gpu/drm/nouveau/dispnv50/disp.c if (ret >= 0 && dpcd >= 0x12) dpcd 40 drivers/gpu/drm/nouveau/nouveau_dp.c nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd) dpcd 45 drivers/gpu/drm/nouveau/nouveau_dp.c if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) dpcd 64 drivers/gpu/drm/nouveau/nouveau_dp.c u8 dpcd[8]; dpcd 71 drivers/gpu/drm/nouveau/nouveau_dp.c ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); dpcd 75 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_bw = 27000 * dpcd[1]; dpcd 76 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; dpcd 79 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); dpcd 92 drivers/gpu/drm/nouveau/nouveau_dp.c nouveau_dp_probe_oui(dev, aux, dpcd); dpcd 94 drivers/gpu/drm/nouveau/nouveau_dp.c ret = nv50_mstm_detect(nv_encoder->dp.mstm, dpcd, nouveau_mst); dpcd 107 drivers/gpu/drm/nouveau/nouveau_encoder.h int nv50_mstm_detect(struct nv50_mstm *, u8 dpcd[8], int allow); dpcd 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) dpcd 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); dpcd 160 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) dpcd 238 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; dpcd 239 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; dpcd 305 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) { dpcd 348 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT; dpcd 349 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE]; dpcd 406 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP; dpcd 520 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd, dpcd 521 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c sizeof(dp->dpcd))) dpcd 24 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h u8 dpcd[16]; dpcd 306 drivers/gpu/drm/radeon/atombios_dp.c const u8 dpcd[DP_DPCD_SIZE], dpcd 312 drivers/gpu/drm/radeon/atombios_dp.c unsigned max_link_rate = drm_dp_max_link_rate(dpcd); dpcd 313 drivers/gpu/drm/radeon/atombios_dp.c unsigned max_lane_num = drm_dp_max_lane_count(dpcd); dpcd 374 drivers/gpu/drm/radeon/atombios_dp.c if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) dpcd 395 drivers/gpu/drm/radeon/atombios_dp.c memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); dpcd 397 drivers/gpu/drm/radeon/atombios_dp.c DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), dpcd 398 drivers/gpu/drm/radeon/atombios_dp.c dig_connector->dpcd); dpcd 405 drivers/gpu/drm/radeon/atombios_dp.c dig_connector->dpcd[0] = 0; dpcd 465 drivers/gpu/drm/radeon/atombios_dp.c ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, dpcd 492 drivers/gpu/drm/radeon/atombios_dp.c ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, dpcd 531 drivers/gpu/drm/radeon/atombios_dp.c if (dig_connector->dpcd[0] >= 0x11) { dpcd 547 drivers/gpu/drm/radeon/atombios_dp.c u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 612 drivers/gpu/drm/radeon/atombios_dp.c if (dp_info->dpcd[3] & 0x1) dpcd 624 drivers/gpu/drm/radeon/atombios_dp.c if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) dpcd 685 drivers/gpu/drm/radeon/atombios_dp.c drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); dpcd 748 drivers/gpu/drm/radeon/atombios_dp.c drm_dp_link_train_channel_eq_delay(dp_info->dpcd); dpcd 844 drivers/gpu/drm/radeon/atombios_dp.c memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); dpcd 527 drivers/gpu/drm/radeon/radeon_dp_mst.c dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); dpcd 528 drivers/gpu/drm/radeon/radeon_dp_mst.c dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); dpcd 678 drivers/gpu/drm/radeon/radeon_dp_mst.c if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) dpcd 490 drivers/gpu/drm/radeon/radeon_mode.h u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 304 drivers/gpu/drm/rockchip/cdn-dp-core.c sink_max = drm_dp_max_lane_count(dp->dpcd); dpcd 308 drivers/gpu/drm/rockchip/cdn-dp-core.c sink_max = drm_dp_max_link_rate(dp->dpcd); dpcd 368 drivers/gpu/drm/rockchip/cdn-dp-core.c ret = cdn_dp_dpcd_read(dp, DP_DPCD_REV, dp->dpcd, dpcd 571 drivers/gpu/drm/rockchip/cdn-dp-core.c u8 sink_lanes = drm_dp_max_lane_count(dp->dpcd); dpcd 101 drivers/gpu/drm/rockchip/cdn-dp-core.h u8 dpcd[DP_RECEIVER_CAP_SIZE]; dpcd 1059 include/drm/drm_dp_helper.h void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); dpcd 1060 include/drm/drm_dp_helper.h void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); dpcd 1128 include/drm/drm_dp_helper.h drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1130 include/drm/drm_dp_helper.h return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); dpcd 1134 include/drm/drm_dp_helper.h drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1136 include/drm/drm_dp_helper.h return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; dpcd 1140 include/drm/drm_dp_helper.h drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1142 include/drm/drm_dp_helper.h return dpcd[DP_DPCD_REV] >= 0x11 && dpcd 1143 include/drm/drm_dp_helper.h (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); dpcd 1147 include/drm/drm_dp_helper.h drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1149 include/drm/drm_dp_helper.h return dpcd[DP_DPCD_REV] >= 0x12 && dpcd 1150 include/drm/drm_dp_helper.h dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; dpcd 1154 include/drm/drm_dp_helper.h drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1156 include/drm/drm_dp_helper.h return dpcd[DP_DPCD_REV] >= 0x14 && dpcd 1157 include/drm/drm_dp_helper.h dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; dpcd 1161 include/drm/drm_dp_helper.h drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1163 include/drm/drm_dp_helper.h return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : dpcd 1168 include/drm/drm_dp_helper.h drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) dpcd 1170 include/drm/drm_dp_helper.h return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; dpcd 1372 include/drm/drm_dp_helper.h int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 1374 include/drm/drm_dp_helper.h int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 1377 include/drm/drm_dp_helper.h void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], dpcd 514 include/drm/drm_dp_mst_helper.h u8 dpcd[DP_RECEIVER_CAP_SIZE];