dp_train_pat 1387 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t dp_train_pat) dp_train_pat 1399 drivers/gpu/drm/gma500/cdv_intel_dp.c dp_train_pat); dp_train_pat 1403 drivers/gpu/drm/gma500/cdv_intel_dp.c dp_train_pat); dp_train_pat 1413 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t dp_train_pat) dp_train_pat 3306 drivers/gpu/drm/i915/display/intel_dp.c u8 dp_train_pat) dp_train_pat 3313 drivers/gpu/drm/i915/display/intel_dp.c if (dp_train_pat & train_pat_mask) dp_train_pat 3315 drivers/gpu/drm/i915/display/intel_dp.c dp_train_pat & train_pat_mask); dp_train_pat 3320 drivers/gpu/drm/i915/display/intel_dp.c if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) dp_train_pat 3326 drivers/gpu/drm/i915/display/intel_dp.c switch (dp_train_pat & train_pat_mask) { dp_train_pat 3350 drivers/gpu/drm/i915/display/intel_dp.c switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { dp_train_pat 3369 drivers/gpu/drm/i915/display/intel_dp.c switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { dp_train_pat 4020 drivers/gpu/drm/i915/display/intel_dp.c u8 dp_train_pat) dp_train_pat 4026 drivers/gpu/drm/i915/display/intel_dp.c _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); dp_train_pat 91 drivers/gpu/drm/i915/display/intel_dp.h u8 dp_train_pat); dp_train_pat 71 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 dp_train_pat) dp_train_pat 76 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); dp_train_pat 78 drivers/gpu/drm/i915/display/intel_dp_link_training.c buf[0] = dp_train_pat; dp_train_pat 79 drivers/gpu/drm/i915/display/intel_dp_link_training.c if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == dp_train_pat 97 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 dp_train_pat) dp_train_pat 101 drivers/gpu/drm/i915/display/intel_dp_link_training.c return intel_dp_set_link_train(intel_dp, dp_train_pat);