dp_reg 1175 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t dp_reg = REG_READ(intel_dp->output_reg); dp_reg 1193 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!(dp_reg & DP_PORT_EN)) { dp_reg 1316 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t dp_reg) dp_reg 1321 drivers/gpu/drm/i915/display/intel_display.c state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); dp_reg 16900 drivers/gpu/drm/i915/display/intel_display.c enum port port, i915_reg_t dp_reg) dp_reg 16902 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(dp_reg); dp_reg 16914 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(dp_reg, val); dp_reg 3098 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t dp_reg, enum port port, dp_reg 3104 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(dp_reg); dp_reg 3417 drivers/gpu/drm/i915/display/intel_dp.c u32 dp_reg = I915_READ(intel_dp->output_reg); dp_reg 3421 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(dp_reg & DP_PORT_EN)) dp_reg 39 drivers/gpu/drm/i915/display/intel_dp.h i915_reg_t dp_reg, enum port port,