dmtc0             296 arch/mips/include/asm/asm.h #define MTC0		dmtc0
dmtc0              34 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_CVMMEMCTL_REG	# Write the cavium mem control register
dmtc0              68 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_CVMCTL_REG
dmtc0              87 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 	dmtc0	v0, CP0_DCACHE_ERR_REG
dmtc0              45 arch/mips/include/asm/mach-ip27/kernel-entry-init.h 	dmtc0	t0, CP0_ENTRYHI