dml 447 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); dml 494 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); dml 495 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dml1_extract_rq_regs(dml, rq_regs, rq_param); dml 497 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dml, dml 1050 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; dml 1051 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; dml 1266 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dml 1268 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; dml 1704 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; dml 1705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; dml 1706 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency; dml 1707 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency; dml 1708 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.ideal_dram_bw_after_urgent_percent = dml 1710 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size; dml 1711 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading; dml 1712 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = dml 1714 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.urgent_out_of_order_return_per_channel_bytes = dml 1716 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels; dml 1717 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size; dml 1718 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; dml 1719 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width; dml 1721 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte; dml 1722 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte; dml 1723 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; dml 1724 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; dml 1725 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte; dml 1726 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes; dml 1727 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size; dml 1728 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size; dml 1729 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size; dml 1730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size; dml 1731 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; dml 1732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes; dml 1733 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp; dml 1734 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size; dml 1735 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size; dml 1736 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; dml 1737 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; dml 1738 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput; dml 1739 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput; dml 1740 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput; dml 1741 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput; dml 1742 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; dml 1743 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; dml 1744 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; dml 1745 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; dml 1747 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin; dml 1748 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor; dml 1749 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; dml 1750 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dml 1752 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.bug_forcing_LC_req_same_size_fixed = dml 1754 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency; dml 1243 drivers/gpu/drm/amd/display/dc/core/dc.c memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); dml 2306 drivers/gpu/drm/amd/display/dc/core/dc.c struct display_mode_lib *dml; dml 2328 drivers/gpu/drm/amd/display/dc/core/dc.c dml = kzalloc(sizeof(struct display_mode_lib), dml 2331 drivers/gpu/drm/amd/display/dc/core/dc.c ASSERT(dml); dml 2332 drivers/gpu/drm/amd/display/dc/core/dc.c if (!dml) dml 2338 drivers/gpu/drm/amd/display/dc/core/dc.c memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib)); dml 2345 drivers/gpu/drm/amd/display/dc/core/dc.c dc->current_state->bw_ctx.dml = *dml; dml 2347 drivers/gpu/drm/amd/display/dc/core/dc.c kfree(dml); dml 490 drivers/gpu/drm/amd/display/dc/dc.h struct display_mode_lib dml; dml 1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); dml 1389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct display_mode_lib *dml = &dc->dml; dml 1391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dml->ip.max_num_dpp = 3; dml 1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->dml.ip.max_num_dpp = pool->base.pipe_count; dml 2232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c bool odm_capable = context->bw_ctx.dml.ip.odm_capable; dml 2456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.ip.odm_capable = 0; dml 2458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); dml 2460 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.ip.odm_capable = odm_capable; dml 2464 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel <= context->bw_ctx.dml.soc.num_states) dml 2467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = context->bw_ctx.dml.soc.num_states + 1; dml 2471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable) dml 2472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); dml 2474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (vlevel > context->bw_ctx.dml.soc.num_states) dml 2520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++) dml 2521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1) dml 2539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true; dml 2540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; dml 2542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) dml 2543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; dml 2544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { dml 2570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) { dml 2573 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.maxMpcComb = 0; dml 2575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2; dml 2579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) dml 2590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { dml 2610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = dml 2642 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; dml 2646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; dml 2647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) dml 2649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; dml 2655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; dml 2656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) dml 2658 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]]; dml 2664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; dml 2665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; dml 2687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; dml 2688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; dml 2693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; dml 2694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; dml 2696 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2704 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; dml 2705 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; dml 2707 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2708 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2709 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2710 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2711 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; dml 2716 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; dml 2718 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2719 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2720 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2721 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2722 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2725 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; dml 2726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; dml 2727 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2728 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2729 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2730 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; dml 2746 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; dml 2747 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; dml 2748 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; dml 2749 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; dml 2750 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; dml 2753 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] dml 2770 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; dml 2771 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; dml 2772 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; dml 2773 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; dml 2785 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; dml 2786 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit]; dml 2787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit]; dml 2788 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit]; dml 2812 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; dml 2813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; dml 2816 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; dml 2821 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, dml 2831 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, dml 2877 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); dml 2897 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; dml 2907 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || dml 2914 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; dml 2928 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); dml 2929 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; dml 3568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); dml 952 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct display_mode_lib *dml, dml 956 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; dml 958 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ASSERT(vlevel < dml->soc.num_states); dml 961 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; dml 962 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; dml 964 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; dml 966 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; dml 967 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; dml 968 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; dml 969 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; dml 970 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; dml 972 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; dml 973 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; dml 975 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; dml 998 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb]; dml 1002 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; dml 1003 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) dml 1005 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; dml 1011 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; dml 1012 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) dml 1014 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]]; dml 1042 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &context->bw_ctx.dml, pipes, pipe_cnt); dml 1047 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &context->bw_ctx.dml, pipes, pipe_cnt); dml 1052 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &context->bw_ctx.dml, pipes, pipe_cnt); dml 1058 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &context->bw_ctx.dml, pipes, pipe_cnt); dml 1101 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); dml 1539 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21); dml 368 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct display_mode_lib dml; dml 49 net/packet/diag.c struct packet_diag_mclist *dml; dml 51 net/packet/diag.c dml = nla_reserve_nohdr(nlskb, sizeof(*dml)); dml 52 net/packet/diag.c if (!dml) { dml 58 net/packet/diag.c dml->pdmc_index = ml->ifindex; dml 59 net/packet/diag.c dml->pdmc_type = ml->type; dml 60 net/packet/diag.c dml->pdmc_alen = ml->alen; dml 61 net/packet/diag.c dml->pdmc_count = ml->count; dml 62 net/packet/diag.c BUILD_BUG_ON(sizeof(dml->pdmc_addr) != sizeof(ml->addr)); dml 63 net/packet/diag.c memcpy(dml->pdmc_addr, ml->addr, sizeof(ml->addr));