dmif               93 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h 	int32_t dmif;
dmif              115 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
dmif              121 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
dmif              127 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
dmif              133 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
dmif              139 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
dmif              145 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
dmif               85 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
dmif               91 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c 					+ DCE110TG_FROM_TG(tg)->offsets.dmif;