dmcu_dce           41 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	(dmcu_dce->regs->reg)
dmcu_dce           45 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
dmcu_dce           48 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->base.ctx
dmcu_dce           73 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce           98 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          121 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          162 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          272 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          289 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          324 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          351 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          372 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          441 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          483 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          510 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          567 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          691 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          736 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          759 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
dmcu_dce          822 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce,
dmcu_dce          828 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dmcu *base = &dmcu_dce->base;
dmcu_dce          834 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->regs = regs;
dmcu_dce          835 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->dmcu_shift = dmcu_shift;
dmcu_dce          836 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->dmcu_mask = dmcu_mask;
dmcu_dce          845 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
dmcu_dce          847 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu_dce == NULL) {
dmcu_dce          853 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
dmcu_dce          855 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->base.funcs = &dce_funcs;
dmcu_dce          857 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	return &dmcu_dce->base;
dmcu_dce          867 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
dmcu_dce          869 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu_dce == NULL) {
dmcu_dce          875 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
dmcu_dce          877 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->base.funcs = &dcn10_funcs;
dmcu_dce          879 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	return &dmcu_dce->base;
dmcu_dce          890 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
dmcu_dce          892 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu_dce == NULL) {
dmcu_dce          898 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
dmcu_dce          900 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dmcu_dce->base.funcs = &dcn20_funcs;
dmcu_dce          902 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	return &dmcu_dce->base;
dmcu_dce          908 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
dmcu_dce          910 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (dmcu_dce->base.dmcu_state == DMCU_RUNNING)
dmcu_dce          911 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		dmcu_dce->base.funcs->set_psr_enable(*dmcu, false, true);
dmcu_dce          913 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	kfree(dmcu_dce);