dmc_header 375 drivers/gpu/drm/i915/intel_csr.c const struct intel_dmc_header_base *dmc_header, dmc_header 394 drivers/gpu/drm/i915/intel_csr.c if (dmc_header->header_ver == 3) { dmc_header 396 drivers/gpu/drm/i915/intel_csr.c (const struct intel_dmc_header_v3 *)dmc_header; dmc_header 406 drivers/gpu/drm/i915/intel_csr.c header_len_bytes = dmc_header->header_len * 4; dmc_header 408 drivers/gpu/drm/i915/intel_csr.c } else if (dmc_header->header_ver == 1) { dmc_header 410 drivers/gpu/drm/i915/intel_csr.c (const struct intel_dmc_header_v1 *)dmc_header; dmc_header 419 drivers/gpu/drm/i915/intel_csr.c header_len_bytes = dmc_header->header_len; dmc_header 423 drivers/gpu/drm/i915/intel_csr.c dmc_header->header_ver); dmc_header 454 drivers/gpu/drm/i915/intel_csr.c payload_size = dmc_header->fw_size * 4; dmc_header 462 drivers/gpu/drm/i915/intel_csr.c csr->dmc_fw_size = dmc_header->fw_size; dmc_header 470 drivers/gpu/drm/i915/intel_csr.c payload = (u8 *)(dmc_header) + header_len_bytes; dmc_header 578 drivers/gpu/drm/i915/intel_csr.c struct intel_dmc_header_base *dmc_header; dmc_header 604 drivers/gpu/drm/i915/intel_csr.c dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount]; dmc_header 605 drivers/gpu/drm/i915/intel_csr.c parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);