dmaobj             37 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	struct nvkm_dmaobj *dmaobj = NULL;
dmaobj             40 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	ret = dma->func->class_new(dma, oclass, data, size, &dmaobj);
dmaobj             41 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	if (dmaobj)
dmaobj             42 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 		*pobject = &dmaobj->object;
dmaobj             51 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	struct nvkm_dmaobj *dmaobj = nvkm_dmaobj(base);
dmaobj             52 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	return dmaobj->func->bind(dmaobj, gpuobj, align, pgpuobj);
dmaobj             70 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		 struct nvkm_dmaobj *dmaobj)
dmaobj             84 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	nvkm_object_ctor(&nvkm_dmaobj_func, oclass, &dmaobj->object);
dmaobj             85 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	dmaobj->func = func;
dmaobj             86 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	dmaobj->dma = dma;
dmaobj             94 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = args->v0.target;
dmaobj             95 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = args->v0.access;
dmaobj             96 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->start  = args->v0.start;
dmaobj             97 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->limit  = args->v0.limit;
dmaobj            104 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	if (dmaobj->start > dmaobj->limit)
dmaobj            107 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	switch (dmaobj->target) {
dmaobj            109 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = NV_MEM_TARGET_VM;
dmaobj            113 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 			if (dmaobj->limit >= fb->ram->size - instmem->reserved)
dmaobj            118 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = NV_MEM_TARGET_VRAM;
dmaobj            123 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = NV_MEM_TARGET_PCI;
dmaobj            129 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
dmaobj            135 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	switch (dmaobj->access) {
dmaobj            137 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = NV_MEM_ACCESS_VM;
dmaobj            140 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = NV_MEM_ACCESS_RO;
dmaobj            143 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = NV_MEM_ACCESS_WO;
dmaobj            146 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		dmaobj->access = NV_MEM_ACCESS_RW;
dmaobj             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	struct gf100_dmaobj *dmaobj = gf100_dmaobj(base);
dmaobj             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
dmaobj             51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
dmaobj             52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
dmaobj             53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
dmaobj             54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
dmaobj             55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 					  upper_32_bits(dmaobj->base.start));
dmaobj             57 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
dmaobj             77 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	struct gf100_dmaobj *dmaobj;
dmaobj             81 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
dmaobj             83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	*pdmaobj = &dmaobj->base;
dmaobj             86 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 			       &data, &size, &dmaobj->base);
dmaobj            103 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
dmaobj            117 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass;
dmaobj            118 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	dmaobj->flags5 |= (unkn << 16);
dmaobj            120 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	switch (dmaobj->base.target) {
dmaobj            122 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00000000;
dmaobj            125 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00010000;
dmaobj            128 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00020000;
dmaobj            131 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00030000;
dmaobj            137 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	switch (dmaobj->base.access) {
dmaobj            141 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00040000;
dmaobj            145 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		dmaobj->flags0 |= 0x00080000;
dmaobj             43 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	struct gf119_dmaobj *dmaobj = gf119_dmaobj(base);
dmaobj             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
dmaobj             50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
dmaobj             51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
dmaobj             52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
dmaobj             75 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	struct gf119_dmaobj *dmaobj;
dmaobj             79 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
dmaobj             81 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	*pdmaobj = &dmaobj->base;
dmaobj             84 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 			       &data, &size, &dmaobj->base);
dmaobj            100 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
dmaobj            112 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	dmaobj->flags0 = (kind << 20) | (page << 6);
dmaobj            114 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	switch (dmaobj->base.target) {
dmaobj            116 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		dmaobj->flags0 |= 0x00000009;
dmaobj             41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	struct gv100_dmaobj *dmaobj = gv100_dmaobj(base);
dmaobj             42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
dmaobj             43 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	u64 start = dmaobj->base.start >> 8;
dmaobj             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	u64 limit = dmaobj->base.limit >> 8;
dmaobj             50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
dmaobj             74 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	struct gv100_dmaobj *dmaobj;
dmaobj             78 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
dmaobj             80 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	*pdmaobj = &dmaobj->base;
dmaobj             83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 			       &data, &size, &dmaobj->base);
dmaobj            105 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		dmaobj->flags0 |= 0x00100000;
dmaobj            107 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		dmaobj->flags0 |= 0x00000040;
dmaobj            108 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	dmaobj->flags0 |= 0x00000004; /* rw */
dmaobj            110 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	switch (dmaobj->base.target) {
dmaobj            111 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	case NV_MEM_TARGET_VRAM       : dmaobj->flags0 |= 0x00000001; break;
dmaobj            112 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	case NV_MEM_TARGET_PCI        : dmaobj->flags0 |= 0x00000002; break;
dmaobj            113 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	case NV_MEM_TARGET_PCI_NOSNOOP: dmaobj->flags0 |= 0x00000003; break;
dmaobj             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	struct nv04_dmaobj *dmaobj = nv04_dmaobj(base);
dmaobj             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
dmaobj             46 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	u64 offset = dmaobj->base.start & 0xfffff000;
dmaobj             47 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	u64 adjust = dmaobj->base.start & 0x00000fff;
dmaobj             48 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	u32 length = dmaobj->base.limit - dmaobj->base.start;
dmaobj             51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	if (dmaobj->clone) {
dmaobj             54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		if (!dmaobj->base.start)
dmaobj             65 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
dmaobj             67 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
dmaobj             68 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
dmaobj             85 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	struct nv04_dmaobj *dmaobj;
dmaobj             88 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
dmaobj             90 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	*pdmaobj = &dmaobj->base;
dmaobj             93 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 			       &data, &size, &dmaobj->base);
dmaobj             97 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	if (dmaobj->base.target == NV_MEM_TARGET_VM) {
dmaobj             99 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 			dmaobj->clone = true;
dmaobj            100 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->base.target = NV_MEM_TARGET_PCI;
dmaobj            101 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->base.access = NV_MEM_ACCESS_RW;
dmaobj            104 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	dmaobj->flags0 = oclass->base.oclass;
dmaobj            105 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	switch (dmaobj->base.target) {
dmaobj            107 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags0 |= 0x00003000;
dmaobj            110 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags0 |= 0x00023000;
dmaobj            113 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags0 |= 0x00033000;
dmaobj            119 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	switch (dmaobj->base.access) {
dmaobj            121 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags0 |= 0x00004000;
dmaobj            124 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags0 |= 0x00008000;
dmaobj            127 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		dmaobj->flags2 |= 0x00000002;
dmaobj             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	struct nv50_dmaobj *dmaobj = nv50_dmaobj(base);
dmaobj             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
dmaobj             51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
dmaobj             52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
dmaobj             53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
dmaobj             54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
dmaobj             55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 					  upper_32_bits(dmaobj->base.start));
dmaobj             57 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
dmaobj             77 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	struct nv50_dmaobj *dmaobj;
dmaobj             81 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
dmaobj             83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	*pdmaobj = &dmaobj->base;
dmaobj             86 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 			       &data, &size, &dmaobj->base);
dmaobj            105 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
dmaobj            121 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	dmaobj->flags0 = (comp << 29) | (kind << 22) | (user << 20) |
dmaobj            123 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	dmaobj->flags5 = (part << 16);
dmaobj            125 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	switch (dmaobj->base.target) {
dmaobj            127 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00000000;
dmaobj            130 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00010000;
dmaobj            133 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00020000;
dmaobj            136 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00030000;
dmaobj            142 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	switch (dmaobj->base.access) {
dmaobj            146 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00040000;
dmaobj            150 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		dmaobj->flags0 |= 0x00080000;
dmaobj            361 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_dmaobj *dmaobj;
dmaobj            378 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		dmaobj = nvkm_dmaobj_search(client, push);
dmaobj            379 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		if (IS_ERR(dmaobj))
dmaobj            380 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			return PTR_ERR(dmaobj);
dmaobj            382 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16,