dma_cntl1        7038 drivers/gpu/drm/radeon/cik.c 	u32 dma_cntl, dma_cntl1;
dma_cntl1        7064 drivers/gpu/drm/radeon/cik.c 	dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
dma_cntl1        7174 drivers/gpu/drm/radeon/cik.c 		dma_cntl1 |= TRAP_ENABLE;
dma_cntl1        7235 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
dma_cntl1        4497 drivers/gpu/drm/radeon/evergreen.c 	u32 dma_cntl, dma_cntl1 = 0;
dma_cntl1        4549 drivers/gpu/drm/radeon/evergreen.c 		dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
dma_cntl1        4552 drivers/gpu/drm/radeon/evergreen.c 			dma_cntl1 |= TRAP_ENABLE;
dma_cntl1        4571 drivers/gpu/drm/radeon/evergreen.c 		WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
dma_cntl1        6056 drivers/gpu/drm/radeon/si.c 	u32 dma_cntl, dma_cntl1;
dma_cntl1        6075 drivers/gpu/drm/radeon/si.c 	dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
dma_cntl1        6100 drivers/gpu/drm/radeon/si.c 		dma_cntl1 |= TRAP_ENABLE;
dma_cntl1        6108 drivers/gpu/drm/radeon/si.c 	WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);