dma_base_and_ceiling   68 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	u64 dma_base_and_ceiling;
dma_base_and_ceiling   86 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	dma_base_and_ceiling = (u64)end << 32 | start;
dma_base_and_ceiling   87 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);