dlg_vblank_end 586 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); dlg_vblank_end 866 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); dlg_vblank_end 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, dlg_vblank_end 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, dlg_vblank_end 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); dlg_vblank_end 1064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); dlg_vblank_end 920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits dlg_vblank_end 920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits dlg_vblank_end 967 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits dlg_vblank_end 410 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int dlg_vblank_end; dlg_vblank_end 203 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dlg_vblank_end); dlg_vblank_end 1142 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */