dlg_regs 448 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; dlg_regs 459 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c memset(dlg_regs, 0, sizeof(*dlg_regs)); dlg_regs 498 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dlg_regs, dlg_regs 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; dlg_regs 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, dlg_regs 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, dlg_regs 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, dlg_regs 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, dlg_regs 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, dlg_regs 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, dlg_regs 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, dlg_regs 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l, dlg_regs 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, dlg_regs 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, dlg_regs 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, dlg_regs 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l, dlg_regs 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l, dlg_regs 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l, dlg_regs 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, dlg_regs 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, dlg_regs 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay, dlg_regs 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->xfc_reg_remote_surface_flip_latency); dlg_regs 2324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, dlg_regs 2330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, dlg_regs 2643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->dlg_regs, dlg_regs 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; dlg_regs 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, dlg_regs 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, dlg_regs 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, dlg_regs 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, dlg_regs 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, dlg_regs 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, dlg_regs 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l, dlg_regs 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l, dlg_regs 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, dlg_regs 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, dlg_regs 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, dlg_regs 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l, dlg_regs 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l, dlg_regs 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l, dlg_regs 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, dlg_regs 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, dlg_regs 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay, dlg_regs 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->xfc_reg_remote_surface_flip_latency); dlg_regs 1241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->dlg_regs, dlg_regs 1346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->dlg_regs, dlg_regs 2822 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &context->res_ctx.pipe_ctx[i].dlg_regs, dlg_regs 1564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_dlg_regs_st *dlg_regs, dlg_regs 1606 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dlg_regs, dlg_regs 63 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h display_dlg_regs_st *dlg_regs, dlg_regs 1564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_dlg_regs_st *dlg_regs, dlg_regs 1606 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dlg_regs, dlg_regs 63 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h display_dlg_regs_st *dlg_regs, dlg_regs 1665 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_dlg_regs_st *dlg_regs, dlg_regs 1711 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dlg_regs, dlg_regs 62 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h display_dlg_regs_st *dlg_regs, dlg_regs 51 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h display_dlg_regs_st *dlg_regs, dlg_regs 194 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs) dlg_regs 200 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_h_blank_end); dlg_regs 203 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dlg_vblank_end); dlg_regs 206 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.min_dst_y_next_start); dlg_regs 209 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_htotal); dlg_regs 212 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_x_after_scaler); dlg_regs 215 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_after_scaler); dlg_regs 218 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_prefetch); dlg_regs 221 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_vm_vblank); dlg_regs 224 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_row_vblank); dlg_regs 227 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_vm_flip); dlg_regs 230 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_row_flip); dlg_regs 233 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.ref_freq_to_pix_freq); dlg_regs 236 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.vratio_prefetch); dlg_regs 239 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.vratio_prefetch_c); dlg_regs 242 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_vblank_l); dlg_regs 245 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_vblank_c); dlg_regs 248 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_vblank_l); dlg_regs 251 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_vblank_c); dlg_regs 254 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_flip_l); dlg_regs 257 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_flip_c); dlg_regs 260 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_flip_l); dlg_regs 263 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_flip_c); dlg_regs 266 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_pte_row_nom_l); dlg_regs 269 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_pte_row_nom_c); dlg_regs 272 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_nom_l); dlg_regs 275 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_pte_group_nom_c); dlg_regs 278 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_meta_row_nom_l); dlg_regs 281 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_per_meta_row_nom_c); dlg_regs 284 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_nom_l); dlg_regs 287 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_meta_chunk_nom_c); dlg_regs 290 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_line_delivery_pre_l); dlg_regs 293 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_line_delivery_pre_c); dlg_regs 296 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_line_delivery_l); dlg_regs 299 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_line_delivery_c); dlg_regs 302 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.chunk_hdl_adjust_cur0); dlg_regs 305 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_offset_cur1); dlg_regs 308 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.chunk_hdl_adjust_cur1); dlg_regs 311 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.vready_after_vcount0); dlg_regs 314 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.dst_y_delta_drq_limit); dlg_regs 317 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.xfc_reg_transfer_delay); dlg_regs 320 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.xfc_reg_precharge_delay); dlg_regs 323 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.xfc_reg_remote_surface_flip_latency); dlg_regs 326 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_vm_dmdata); dlg_regs 44 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs); dlg_regs 58 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h struct _vcs_dpi_display_dlg_regs_st *dlg_regs, dlg_regs 307 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct _vcs_dpi_display_dlg_regs_st dlg_regs; dlg_regs 71 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct _vcs_dpi_display_dlg_regs_st *dlg_regs, dlg_regs 78 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct _vcs_dpi_display_dlg_regs_st *dlg_regs, dlg_regs 95 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h struct _vcs_dpi_display_dlg_regs_st *dlg_regs,