divsel           4997 drivers/gpu/drm/i915/display/intel_display.c 	u32 divsel, phaseinc, auxdiv, phasedir = 0;
divsel           5015 drivers/gpu/drm/i915/display/intel_display.c 		divsel = (desired_divisor / iclk_pi_range) - 2;
divsel           5022 drivers/gpu/drm/i915/display/intel_display.c 		if (divsel <= 0x7f)
divsel           5027 drivers/gpu/drm/i915/display/intel_display.c 	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
divsel           5035 drivers/gpu/drm/i915/display/intel_display.c 			divsel,
divsel           5044 drivers/gpu/drm/i915/display/intel_display.c 	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
divsel           5072 drivers/gpu/drm/i915/display/intel_display.c 	u32 divsel, phaseinc, auxdiv;
divsel           5090 drivers/gpu/drm/i915/display/intel_display.c 	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
divsel           5101 drivers/gpu/drm/i915/display/intel_display.c 	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
divsel            504 drivers/mfd/db8500-prcmu.c 	u32 divsel;
divsel            511 drivers/mfd/db8500-prcmu.c 		.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
divsel            516 drivers/mfd/db8500-prcmu.c 		.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
divsel           1424 drivers/mfd/db8500-prcmu.c 	val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
divsel           1578 drivers/mfd/db8500-prcmu.c 	u32 divsel;
divsel           1581 drivers/mfd/db8500-prcmu.c 	divsel = readl(PRCM_DSI_PLLOUT_SEL);
divsel           1582 drivers/mfd/db8500-prcmu.c 	divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
divsel           1584 drivers/mfd/db8500-prcmu.c 	if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
divsel           1585 drivers/mfd/db8500-prcmu.c 		divsel = dsiclk[n].divsel;
divsel           1587 drivers/mfd/db8500-prcmu.c 		dsiclk[n].divsel = divsel;
divsel           1589 drivers/mfd/db8500-prcmu.c 	switch (divsel) {
divsel           1957 drivers/mfd/db8500-prcmu.c 	dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
divsel           1963 drivers/mfd/db8500-prcmu.c 	val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
divsel            741 sound/soc/codecs/wm9713.c 	u32 divsel:1;
divsel            764 sound/soc/codecs/wm9713.c 		pll_div->divsel = 1;
divsel            773 sound/soc/codecs/wm9713.c 		pll_div->divsel = 0;
divsel            834 sound/soc/codecs/wm9713.c 			(pll_div.divsel << 9) | (pll_div.divctl << 8);
divsel            839 sound/soc/codecs/wm9713.c 			(pll_div.divsel << 9) | (pll_div.divctl << 8);