divs 120 arch/arm/plat-samsung/include/plat/cpu-freq-core.h struct s3c_clkdivs divs; divs 17 arch/mips/include/asm/mips-r2-to-r6-emul.h u64 divs; divs 463 arch/mips/kernel/mips-r2-to-r6-emul.c MIPS_R2_STATS(divs); divs 485 arch/mips/kernel/mips-r2-to-r6-emul.c MIPS_R2_STATS(divs); divs 574 arch/mips/kernel/mips-r2-to-r6-emul.c MIPS_R2_STATS(divs); divs 599 arch/mips/kernel/mips-r2-to-r6-emul.c MIPS_R2_STATS(divs); divs 2252 arch/mips/kernel/mips-r2-to-r6-emul.c (unsigned long)__this_cpu_read(mipsr2emustats.divs), divs 2253 arch/mips/kernel/mips-r2-to-r6-emul.c (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); divs 2314 arch/mips/kernel/mips-r2-to-r6-emul.c __this_cpu_write((mipsr2emustats).divs, 0); divs 2315 arch/mips/kernel/mips-r2-to-r6-emul.c __this_cpu_write((mipsr2bdemustats).divs, 0); divs 414 crypto/testmgr.c static unsigned int count_test_sg_divisions(const struct test_sg_division *divs) divs 420 crypto/testmgr.c remaining -= divs[ndivs++].proportion_of_total; divs 429 crypto/testmgr.c static bool valid_sg_divisions(const struct test_sg_division *divs, divs 436 crypto/testmgr.c if (divs[i].proportion_of_total <= 0 || divs 437 crypto/testmgr.c divs[i].proportion_of_total > TEST_SG_TOTAL - total) divs 439 crypto/testmgr.c total += divs[i].proportion_of_total; divs 440 crypto/testmgr.c if (divs[i].flush_type != FLUSH_TYPE_NONE) divs 442 crypto/testmgr.c if (divs[i].nosimd) divs 446 crypto/testmgr.c memchr_inv(&divs[i], 0, (count - i) * sizeof(divs[0])) == NULL; divs 528 crypto/testmgr.c const struct test_sg_division *divs, divs 538 crypto/testmgr.c const unsigned int ndivs = count_test_sg_divisions(divs); divs 551 crypto/testmgr.c (total_len * divs[i].proportion_of_total + divs 555 crypto/testmgr.c partitions[tsgl->nents].div = &divs[i]; divs 562 crypto/testmgr.c partitions[tsgl->nents].div = &divs[0]; divs 829 crypto/testmgr.c static char *generate_random_sgl_divisions(struct test_sg_division *divs, divs 833 crypto/testmgr.c struct test_sg_division *div = divs; divs 840 crypto/testmgr.c if (div == &divs[max_divs - 1] || prandom_u32() % 2 == 0) divs 1039 crypto/testmgr.c const struct test_sg_division *divs[XBUFSIZE]) divs 1048 crypto/testmgr.c &input, divs); divs 1099 crypto/testmgr.c const struct test_sg_division *divs[XBUFSIZE]; divs 1123 crypto/testmgr.c err = build_hash_sglist(tsgl, vec, cfg, alignmask, divs); divs 1176 crypto/testmgr.c if (divs[i]->nosimd) divs 1180 crypto/testmgr.c if (divs[i]->nosimd) divs 1188 crypto/testmgr.c if (divs[i]->nosimd) divs 1192 crypto/testmgr.c if (divs[i]->nosimd) divs 1197 crypto/testmgr.c if (divs[i]->flush_type == FLUSH_TYPE_REIMPORT) { divs 1283 crypto/testmgr.c const struct test_sg_division *divs[XBUFSIZE]; divs 1310 crypto/testmgr.c err = build_hash_sglist(tsgl, vec, cfg, alignmask, divs); divs 1358 crypto/testmgr.c if (divs[i]->flush_type != FLUSH_TYPE_NONE && divs 1366 crypto/testmgr.c divs[i]->nosimd); divs 1375 crypto/testmgr.c if (divs[i]->flush_type == FLUSH_TYPE_REIMPORT) { divs 108 drivers/clk/rockchip/clk-cpu.c for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { divs 109 drivers/clk/rockchip/clk-cpu.c const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; divs 90 drivers/clk/rockchip/clk-px30.c .divs = { \ divs 93 drivers/clk/rockchip/clk-rk3036.c .divs = { \ divs 92 drivers/clk/rockchip/clk-rk3128.c .divs = { \ divs 131 drivers/clk/rockchip/clk-rk3188.c .divs = { \ divs 169 drivers/clk/rockchip/clk-rk3188.c .divs = { \ divs 93 drivers/clk/rockchip/clk-rk3228.c .divs = { \ divs 153 drivers/clk/rockchip/clk-rk3288.c .divs = { \ divs 86 drivers/clk/rockchip/clk-rk3308.c .divs = { \ divs 105 drivers/clk/rockchip/clk-rk3328.c .divs = { \ divs 202 drivers/clk/rockchip/clk-rk3368.c .divs = { \ divs 212 drivers/clk/rockchip/clk-rk3368.c .divs = { \ divs 337 drivers/clk/rockchip/clk-rk3399.c .divs = { \ divs 347 drivers/clk/rockchip/clk-rk3399.c .divs = { \ divs 82 drivers/clk/rockchip/clk-rv1108.c .divs = { \ divs 328 drivers/clk/rockchip/clk.h struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; divs 34 drivers/cpufreq/s3c2410-cpufreq.c if (cfg->divs.h_divisor == 2) divs 37 drivers/cpufreq/s3c2410-cpufreq.c if (cfg->divs.p_divisor != cfg->divs.h_divisor) divs 76 drivers/cpufreq/s3c2410-cpufreq.c cfg->divs.p_divisor = pdiv; divs 77 drivers/cpufreq/s3c2410-cpufreq.c cfg->divs.h_divisor = hdiv; divs 69 drivers/cpufreq/s3c2412-cpufreq.c cfg->divs.arm_divisor = armdiv; divs 79 drivers/cpufreq/s3c2412-cpufreq.c cfg->divs.dvs = dvs = armclk < armdiv_clk; divs 85 drivers/cpufreq/s3c2412-cpufreq.c __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); divs 106 drivers/cpufreq/s3c2412-cpufreq.c cfg->divs.h_divisor = hdiv * armdiv; divs 107 drivers/cpufreq/s3c2412-cpufreq.c cfg->divs.p_divisor = pdiv * armdiv; divs 128 drivers/cpufreq/s3c2412-cpufreq.c if (cfg->divs.arm_divisor == 2) divs 131 drivers/cpufreq/s3c2412-cpufreq.c clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); divs 133 drivers/cpufreq/s3c2412-cpufreq.c if (cfg->divs.p_divisor != cfg->divs.h_divisor) divs 139 drivers/cpufreq/s3c2412-cpufreq.c clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); divs 111 drivers/cpufreq/s3c2440-cpufreq.c cfg->divs.dvs = 1; divs 114 drivers/cpufreq/s3c2440-cpufreq.c cfg->divs.dvs = 0; divs 120 drivers/cpufreq/s3c2440-cpufreq.c cfg->divs.h_divisor = hdiv; divs 121 drivers/cpufreq/s3c2440-cpufreq.c cfg->divs.p_divisor = pdiv; divs 144 drivers/cpufreq/s3c2440-cpufreq.c cfg->divs.h_divisor, cfg->divs.p_divisor); divs 152 drivers/cpufreq/s3c2440-cpufreq.c switch (cfg->divs.h_divisor) { divs 177 drivers/cpufreq/s3c2440-cpufreq.c if (cfg->divs.p_divisor != cfg->divs.h_divisor) divs 193 drivers/cpufreq/s3c2440-cpufreq.c clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); divs 197 drivers/cpufreq/s3c2440-cpufreq.c int *divs, divs 205 drivers/cpufreq/s3c2440-cpufreq.c for (div = *divs; div > 0; div = *divs++) { divs 85 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c cfg->divs.h_divisor, cfg->divs.p_divisor, divs 86 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); divs 76 drivers/cpufreq/s3c24xx-cpufreq.c cfg->divs.h_divisor = fclk / hclk; divs 77 drivers/cpufreq/s3c24xx-cpufreq.c cfg->divs.p_divisor = fclk / pclk; divs 85 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.hclk = pll / cfg->divs.h_divisor; divs 86 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.pclk = pll / cfg->divs.p_divisor; divs 105 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.hclk, cfg->divs.h_divisor, divs 106 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.pclk, cfg->divs.p_divisor); divs 1318 drivers/gpu/drm/msm/edp/edp_ctrl.c const struct edp_pixel_clk_div *divs; divs 1324 drivers/gpu/drm/msm/edp/edp_ctrl.c divs = clk_divs[0]; divs 1326 drivers/gpu/drm/msm/edp/edp_ctrl.c divs = clk_divs[1]; divs 1333 drivers/gpu/drm/msm/edp/edp_ctrl.c clk_err = abs(divs[i].rate - pixel_rate); divs 1334 drivers/gpu/drm/msm/edp/edp_ctrl.c if ((divs[i].rate * err / 100) >= clk_err) { divs 1336 drivers/gpu/drm/msm/edp/edp_ctrl.c *pm = divs[i].m; divs 1338 drivers/gpu/drm/msm/edp/edp_ctrl.c *pn = divs[i].n; divs 212 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c int divs = 0; divs 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); divs 223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c clk->cctrl = divs << 16; divs 247 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c out = calc_P((core << 1), shader, &divs); divs 251 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c (divs + P2) <= 7) { divs 253 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c clk->sctrl = (divs + P2) << 16; divs 262 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c out = calc_P(core, vdec, &divs); divs 266 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c clk->vdiv = divs << 16; divs 447 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, divs, divsm, divsv); divs 44 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c u32 divs, duty; divs 47 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); divs 48 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c if (ret == 0 && divs) { divs 49 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs = max(divs, duty); divs 51 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c duty = divs - duty; divs 52 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c return (duty * 100) / divs; divs 63 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c u32 divs, duty; divs 66 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs = fan->base.perf.pwm_divisor; divs 68 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs = 1; divs 70 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs = therm->func->pwm_clock(therm, fan->func.line); divs 71 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs /= fan->base.bios.pwm_freq; divs 74 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c duty = ((divs * percent) + 99) / 100; divs 76 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c duty = divs - duty; divs 78 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); divs 91 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c u32 divs, duty; divs 97 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c therm->func->pwm_get(therm, func->line, &divs, &duty) == -ENODEV) divs 67 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) divs 75 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); divs 80 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; divs 89 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) divs 96 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c nvkm_wr32(device, 0x00e114 + (indx * 8), divs); divs 99 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ divs 34 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) divs 37 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; divs 43 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) divs 46 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ divs 121 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) divs 129 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *divs = (reg & 0x00007fff); divs 136 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *divs = nvkm_rd32(device, 0x0015f8); divs 149 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) divs 154 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); divs 157 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c nvkm_wr32(device, 0x0015f8, divs); divs 66 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) divs 74 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); divs 83 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) divs 90 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c nvkm_wr32(device, 0x00e114 + (id * 8), divs); divs 799 drivers/i2c/busses/i2c-s3c2410.c unsigned int *div1, unsigned int *divs) divs 817 drivers/i2c/busses/i2c-s3c2410.c *divs = calc_divs; divs 832 drivers/i2c/busses/i2c-s3c2410.c unsigned int divs, div1; divs 846 drivers/i2c/busses/i2c-s3c2410.c freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); divs 859 drivers/i2c/busses/i2c-s3c2410.c iiccon |= (divs-1);