divq              147 drivers/clk/analogbits/wrpll-cln28hpc.c 	u8 divq = 0;
divq              156 drivers/clk/analogbits/wrpll-cln28hpc.c 		divq = 1;
divq              159 drivers/clk/analogbits/wrpll-cln28hpc.c 		divq = ilog2(MAX_DIVQ_DIVISOR);
divq              162 drivers/clk/analogbits/wrpll-cln28hpc.c 		divq = ilog2(s);
divq              163 drivers/clk/analogbits/wrpll-cln28hpc.c 		*vco_rate = (u64)target_rate << divq;
divq              167 drivers/clk/analogbits/wrpll-cln28hpc.c 	return divq;
divq              227 drivers/clk/analogbits/wrpll-cln28hpc.c 	u8 fbdiv, divq, best_r, r;
divq              255 drivers/clk/analogbits/wrpll-cln28hpc.c 	divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
divq              256 drivers/clk/analogbits/wrpll-cln28hpc.c 	if (!divq)
divq              258 drivers/clk/analogbits/wrpll-cln28hpc.c 	c->divq = divq;
divq              344 drivers/clk/analogbits/wrpll-cln28hpc.c 	n >>= c->divq;
divq               97 drivers/clk/clk-highbank.c 	unsigned long divf, divq, vco_freq, reg;
divq              104 drivers/clk/clk-highbank.c 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
divq              107 drivers/clk/clk-highbank.c 	return vco_freq / (1 << divq);
divq              113 drivers/clk/clk-highbank.c 	u32 divq, divf;
divq              121 drivers/clk/clk-highbank.c 	for (divq = 1; divq <= 6; divq++) {
divq              122 drivers/clk/clk-highbank.c 		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
divq              126 drivers/clk/clk-highbank.c 	vco_freq = rate * (1 << divq);
divq              130 drivers/clk/clk-highbank.c 	*pdivq = divq;
divq              137 drivers/clk/clk-highbank.c 	u32 divq, divf;
divq              140 drivers/clk/clk-highbank.c 	clk_pll_calc(rate, ref_freq, &divq, &divf);
divq              142 drivers/clk/clk-highbank.c 	return (ref_freq * (divf + 1)) / (1 << divq);
divq              149 drivers/clk/clk-highbank.c 	u32 divq, divf;
divq              152 drivers/clk/clk-highbank.c 	clk_pll_calc(rate, parent_rate, &divq, &divf);
divq              162 drivers/clk/clk-highbank.c 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
divq              175 drivers/clk/clk-highbank.c 		reg |= divq << HB_PLL_DIVQ_SHIFT;
divq               99 drivers/clk/imx/clk-frac-pll.c 	u32 val, divff, divfi, divq;
divq              104 drivers/clk/imx/clk-frac-pll.c 	divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
divq              112 drivers/clk/imx/clk-frac-pll.c 	do_div(temp64, divq);
divq              115 drivers/clk/imx/clk-frac-pll.c 	do_div(rate, divq);
divq               73 drivers/clk/imx/clk-sccg-pll.c 	int divq;
divq              136 drivers/clk/imx/clk-sccg-pll.c 	for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX;
divq              137 drivers/clk/imx/clk-sccg-pll.c 	     temp_setup->divq++) {
divq              145 drivers/clk/imx/clk-sccg-pll.c 			do_div(temp_setup->fout, 2 * (temp_setup->divq + 1));
divq              340 drivers/clk/imx/clk-sccg-pll.c 	u32 val, divr1, divf1, divr2, divf2, divq;
divq              348 drivers/clk/imx/clk-sccg-pll.c 	divq = FIELD_GET(PLL_DIVQ_MASK, val);
divq              357 drivers/clk/imx/clk-sccg-pll.c 		do_div(temp64, (divr2 + 1) * (divq + 1));
divq              361 drivers/clk/imx/clk-sccg-pll.c 		do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
divq              387 drivers/clk/imx/clk-sccg-pll.c 	val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq);
divq              248 drivers/clk/sifive/fu540-prci.c 	c->divq = v;
divq              282 drivers/clk/sifive/fu540-prci.c 	r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
divq               38 drivers/clk/socfpga/clk-pll-a10.c 	unsigned long divf, divq, reg;
divq               44 drivers/clk/socfpga/clk-pll-a10.c 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
divq               46 drivers/clk/socfpga/clk-pll-a10.c 	do_div(vco_freq, (1 + divq));
divq               42 drivers/clk/socfpga/clk-pll.c 	unsigned long divf, divq, reg;
divq               52 drivers/clk/socfpga/clk-pll.c 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
divq               54 drivers/clk/socfpga/clk-pll.c 	do_div(vco_freq, (1 + divq));
divq              524 drivers/media/pci/solo6x10/solo6x10-core.c 		u32 divq, divf;
divq              529 drivers/media/pci/solo6x10/solo6x10-core.c 			divq = 3;
divq              532 drivers/media/pci/solo6x10/solo6x10-core.c 			divq = 2;
divq              539 drivers/media/pci/solo6x10/solo6x10-core.c 			       (divq << 12) |
divq               60 include/linux/clk/analogbits-wrpll-cln28hpc.h 	u8 divq;