divil_msr_reg      17 arch/mips/loongson64/common/cs5536/cs5536_isa.c static const u32 divil_msr_reg[6] = {
divil_msr_reg      96 arch/mips/loongson64/common/cs5536/cs5536_isa.c 		_wrmsr(divil_msr_reg[n], hi, lo);
divil_msr_reg     121 arch/mips/loongson64/common/cs5536/cs5536_isa.c 		_rdmsr(divil_msr_reg[n], &hi, &lo);