divider_reg       430 drivers/clk/clk-xgene.c 	void __iomem *divider_reg;	/* CSR for divider */
divider_reg       539 drivers/clk/clk-xgene.c 	if (pclk->param.divider_reg) {
divider_reg       540 drivers/clk/clk-xgene.c 		data = xgene_clk_read(pclk->param.divider_reg +
divider_reg       569 drivers/clk/clk-xgene.c 	if (pclk->param.divider_reg) {
divider_reg       578 drivers/clk/clk-xgene.c 		data = xgene_clk_read(pclk->param.divider_reg +
divider_reg       583 drivers/clk/clk-xgene.c 		xgene_clk_write(data, pclk->param.divider_reg +
divider_reg       604 drivers/clk/clk-xgene.c 	if (pclk->param.divider_reg) {
divider_reg       681 drivers/clk/clk-xgene.c 	parameters.divider_reg = NULL;
divider_reg       698 drivers/clk/clk-xgene.c 			parameters.divider_reg = map_res;
divider_reg       736 drivers/clk/clk-xgene.c 	if (parameters.divider_reg)
divider_reg       737 drivers/clk/clk-xgene.c 		iounmap(parameters.divider_reg);
divider_reg       207 drivers/clk/mediatek/clk-mtk.c 		div->reg = base + mc->divider_reg;
divider_reg        66 drivers/clk/mediatek/clk-mtk.h 	uint32_t divider_reg;
divider_reg       136 drivers/clk/mediatek/clk-mtk.h 		.divider_reg = _div_reg,				\
divider_reg        40 drivers/clk/mvebu/ap-cpu-clk.c 	unsigned int divider_reg;
divider_reg        78 drivers/clk/mvebu/ap-cpu-clk.c 	.divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
divider_reg       112 drivers/clk/mvebu/ap-cpu-clk.c 	.divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
divider_reg       151 drivers/clk/mvebu/ap-cpu-clk.c 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +
divider_reg       167 drivers/clk/mvebu/ap-cpu-clk.c 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +