divf 299 drivers/clk/analogbits/wrpll-cln28hpc.c c->divf = best_f - 1; divf 342 drivers/clk/analogbits/wrpll-cln28hpc.c n = parent_rate * fbdiv * (c->divf + 1); divf 97 drivers/clk/clk-highbank.c unsigned long divf, divq, vco_freq, reg; divf 103 drivers/clk/clk-highbank.c divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT; divf 105 drivers/clk/clk-highbank.c vco_freq = parent_rate * (divf + 1); divf 113 drivers/clk/clk-highbank.c u32 divq, divf; divf 127 drivers/clk/clk-highbank.c divf = (vco_freq + (ref_freq / 2)) / ref_freq; divf 128 drivers/clk/clk-highbank.c divf--; divf 131 drivers/clk/clk-highbank.c *pdivf = divf; divf 137 drivers/clk/clk-highbank.c u32 divq, divf; divf 140 drivers/clk/clk-highbank.c clk_pll_calc(rate, ref_freq, &divq, &divf); divf 142 drivers/clk/clk-highbank.c return (ref_freq * (divf + 1)) / (1 << divq); divf 149 drivers/clk/clk-highbank.c u32 divq, divf; divf 152 drivers/clk/clk-highbank.c clk_pll_calc(rate, parent_rate, &divq, &divf); divf 155 drivers/clk/clk-highbank.c if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) { divf 162 drivers/clk/clk-highbank.c reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); divf 244 drivers/clk/sifive/fu540-prci.c c->divf = v; divf 281 drivers/clk/sifive/fu540-prci.c r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; divf 38 drivers/clk/socfpga/clk-pll-a10.c unsigned long divf, divq, reg; divf 43 drivers/clk/socfpga/clk-pll-a10.c divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; divf 45 drivers/clk/socfpga/clk-pll-a10.c vco_freq = (unsigned long long)parent_rate * (divf + 1); divf 42 drivers/clk/socfpga/clk-pll.c unsigned long divf, divq, reg; divf 51 drivers/clk/socfpga/clk-pll.c divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; divf 53 drivers/clk/socfpga/clk-pll.c vco_freq = (unsigned long long)parent_rate * (divf + 1); divf 256 drivers/ide/ide-proc.c div_factor = setting->divf ? setting->divf(drive) : 1; divf 370 drivers/ide/ide-proc.c div_factor = setting->divf ? setting->divf(drive) : 1; divf 524 drivers/media/pci/solo6x10/solo6x10-core.c u32 divq, divf; divf 530 drivers/media/pci/solo6x10/solo6x10-core.c divf = (solo_dev->clock_mhz * 4) / 3 - 1; divf 533 drivers/media/pci/solo6x10/solo6x10-core.c divf = (solo_dev->clock_mhz * 2) / 3 - 1; divf 540 drivers/media/pci/solo6x10/solo6x10-core.c (divf << 4) | divf 63 include/linux/clk/analogbits-wrpll-cln28hpc.h u16 divf; divf 956 include/linux/ide.h int (*divf)(ide_drive_t *); divf 965 include/linux/ide.h .divf = _divf, \