div_ops 355 drivers/clk/clk-stm32h7.c const struct clk_ops *div_ops; div_ops 366 drivers/clk/clk-stm32h7.c const struct clk_ops *mux_ops, *div_ops, *gate_ops; div_ops 371 drivers/clk/clk-stm32h7.c mux_ops = div_ops = gate_ops = NULL; div_ops 395 drivers/clk/clk-stm32h7.c div_ops = gcfg->div->ops ? div_ops 416 drivers/clk/clk-stm32h7.c composite->div_ops = div_ops; div_ops 1327 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_ops 1350 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_ops 1365 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_ops 1379 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_ops 615 drivers/clk/clk-stm32mp1.c const struct clk_ops *mux_ops, *div_ops, *gate_ops; div_ops 622 drivers/clk/clk-stm32mp1.c div_ops = NULL; div_ops 640 drivers/clk/clk-stm32mp1.c div_ops = &clk_divider_ops; div_ops 643 drivers/clk/clk-stm32mp1.c div_ops = cfg->div->ops; div_ops 659 drivers/clk/clk-stm32mp1.c mux_hw, mux_ops, div_hw, div_ops, div_ops 28 drivers/clk/imx/clk-busy.c const struct clk_ops *div_ops; div_ops 45 drivers/clk/imx/clk-busy.c return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); div_ops 53 drivers/clk/imx/clk-busy.c return busy->div_ops->round_rate(&busy->div.hw, rate, prate); div_ops 62 drivers/clk/imx/clk-busy.c ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); div_ops 95 drivers/clk/imx/clk-busy.c busy->div_ops = &clk_divider_ops; div_ops 157 drivers/clk/mediatek/clk-mtk.c const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL; div_ops 213 drivers/clk/mediatek/clk-mtk.c div_ops = &clk_divider_ops; div_ops 218 drivers/clk/mediatek/clk-mtk.c div_hw, div_ops, div_ops 209 drivers/clk/nxp/clk-lpc18xx-ccu.c const struct clk_ops *div_ops = NULL; div_ops 224 drivers/clk/nxp/clk-lpc18xx-ccu.c div_ops = &clk_divider_ro_ops; div_ops 232 drivers/clk/nxp/clk-lpc18xx-ccu.c div_hw, div_ops, div_ops 174 drivers/clk/rockchip/clk-half-divider.c const struct clk_ops *mux_ops = NULL, *div_ops = NULL, div_ops 213 drivers/clk/rockchip/clk-half-divider.c div_ops = &clk_half_divider_ops; div_ops 218 drivers/clk/rockchip/clk-half-divider.c div ? &div->hw : NULL, div_ops, div_ops 50 drivers/clk/rockchip/clk.c const struct clk_ops *mux_ops = NULL, *div_ops = NULL, div_ops 98 drivers/clk/rockchip/clk.c div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) div_ops 105 drivers/clk/rockchip/clk.c div ? &div->hw : NULL, div_ops, div_ops 221 drivers/clk/rockchip/clk.c const struct clk_ops *div_ops = NULL, *gate_ops = NULL; div_ops 256 drivers/clk/rockchip/clk.c div_ops = &clk_fractional_divider_ops; div_ops 260 drivers/clk/rockchip/clk.c &div->hw, div_ops, div_ops 39 drivers/clk/tegra/clk-periph.c const struct clk_ops *div_ops = periph->div_ops; div_ops 44 drivers/clk/tegra/clk-periph.c return div_ops->recalc_rate(div_hw, parent_rate); div_ops 51 drivers/clk/tegra/clk-periph.c const struct clk_ops *div_ops = periph->div_ops; div_ops 56 drivers/clk/tegra/clk-periph.c return div_ops->round_rate(div_hw, rate, prate); div_ops 63 drivers/clk/tegra/clk-periph.c const struct clk_ops *div_ops = periph->div_ops; div_ops 68 drivers/clk/tegra/clk-periph.c return div_ops->set_rate(div_hw, rate, parent_rate); div_ops 126 drivers/clk/tegra/clk-super.c return super->div_ops->round_rate(div_hw, rate, parent_rate); div_ops 137 drivers/clk/tegra/clk-super.c return super->div_ops->recalc_rate(div_hw, parent_rate); div_ops 148 drivers/clk/tegra/clk-super.c return super->div_ops->set_rate(div_hw, rate, parent_rate); div_ops 223 drivers/clk/tegra/clk-super.c super->div_ops = &tegra_clk_frac_div_ops; div_ops 563 drivers/clk/tegra/clk.h const struct clk_ops *div_ops; div_ops 605 drivers/clk/tegra/clk.h .div_ops = &tegra_clk_frac_div_ops, \ div_ops 677 drivers/clk/tegra/clk.h const struct clk_ops *div_ops;