div_offset 68 drivers/clk/clk-si570.c unsigned int div_offset; div_offset 101 drivers/clk/clk-si570.c err = regmap_bulk_read(data->regmap, SI570_REG_HS_N1 + data->div_offset, div_offset 171 drivers/clk/clk-si570.c data->div_offset, reg, ARRAY_SIZE(reg)); div_offset 292 drivers/clk/clk-si570.c regmap_write(data->regmap, SI570_REG_HS_N1 + data->div_offset, div_offset 426 drivers/clk/clk-si570.c data->div_offset = SI570_DIV_OFFSET_7PPM; div_offset 41 drivers/clk/rockchip/clk.c int div_offset, u8 div_shift, u8 div_width, u8 div_flags, div_offset 90 drivers/clk/rockchip/clk.c if (div_offset) div_offset 91 drivers/clk/rockchip/clk.c div->reg = base + div_offset; div_offset 514 drivers/clk/rockchip/clk.c list->div_offset, list->div_shift, list->div_width, div_offset 414 drivers/clk/rockchip/clk.h int div_offset; div_offset 459 drivers/clk/rockchip/clk.h .div_offset = do, \ div_offset 249 drivers/clk/sirf/clk-atlas7.c u32 div_offset; div_offset 1645 drivers/clk/sirf/clk-atlas7.c div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset, div_offset 73 drivers/clk/socfpga/clk-gate-s10.c unsigned long div_offset, u8 div_width, div_offset 99 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->shift = div_offset; div_offset 234 drivers/clk/socfpga/clk-s10.c clks[i].div_offset, clks[i].div_width, div_offset 56 drivers/clk/socfpga/stratix10-clk.h u8 div_offset; div_offset 68 drivers/clk/tegra/clk-tegra-audio.c u8 div_offset; div_offset 79 drivers/clk/tegra/clk-tegra-audio.c .div_offset = _offset,\ div_offset 239 drivers/clk/tegra/clk-tegra-audio.c 0, 0, data->div_offset, 1, 0, div_offset 18 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u8 div_offset; div_offset 29 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u8 div_offset, div_offset 37 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c for (m = div_offset ?: 1; m < (16 + div_offset); m++) { div_offset 88 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c for (j = tmds->div_offset ?: 1; div_offset 89 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c j < (16 + tmds->div_offset); j++) { div_offset 136 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = ((reg >> 4) & 0xf) + tmds->div_offset; div_offset 151 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset, div_offset 162 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset), div_offset 229 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c tmds->div_offset = hdmi->variant->tmds_clk_div_offset;