div_m             192 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 	u8 div_m;
div_m             195 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 	tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
div_m             200 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 	reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
div_m              90 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 	u8 div_m, div_n;
div_m              93 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 			       ddc->m_offset, &div_m, &div_n);
div_m              96 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 			   SUN4I_HDMI_DDC_CLK_M(div_m) |