div_hw 61 drivers/clk/actions/owl-composite.c return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw, div_hw 70 drivers/clk/actions/owl-composite.c return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw, div_hw 79 drivers/clk/actions/owl-composite.c return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw, div_hw 22 drivers/clk/actions/owl-composite.h struct owl_divider_hw div_hw; div_hw 42 drivers/clk/actions/owl-composite.h .rate.div_hw = _div, \ div_hw 56 drivers/clk/actions/owl-composite.h .rate.div_hw = _div, \ div_hw 17 drivers/clk/actions/owl-divider.c const struct owl_divider_hw *div_hw, div_hw 22 drivers/clk/actions/owl-divider.c div_hw->table, div_hw->width, div_hw 23 drivers/clk/actions/owl-divider.c div_hw->div_flags); div_hw 31 drivers/clk/actions/owl-divider.c return owl_divider_helper_round_rate(&div->common, &div->div_hw, div_hw 36 drivers/clk/actions/owl-divider.c const struct owl_divider_hw *div_hw, div_hw 42 drivers/clk/actions/owl-divider.c regmap_read(common->regmap, div_hw->reg, ®); div_hw 43 drivers/clk/actions/owl-divider.c val = reg >> div_hw->shift; div_hw 44 drivers/clk/actions/owl-divider.c val &= (1 << div_hw->width) - 1; div_hw 47 drivers/clk/actions/owl-divider.c val, div_hw->table, div_hw 48 drivers/clk/actions/owl-divider.c div_hw->div_flags, div_hw 49 drivers/clk/actions/owl-divider.c div_hw->width); div_hw 58 drivers/clk/actions/owl-divider.c &div->div_hw, parent_rate); div_hw 62 drivers/clk/actions/owl-divider.c const struct owl_divider_hw *div_hw, div_hw 69 drivers/clk/actions/owl-divider.c val = divider_get_val(rate, parent_rate, div_hw->table, div_hw 70 drivers/clk/actions/owl-divider.c div_hw->width, 0); div_hw 72 drivers/clk/actions/owl-divider.c regmap_read(common->regmap, div_hw->reg, ®); div_hw 73 drivers/clk/actions/owl-divider.c reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift); div_hw 75 drivers/clk/actions/owl-divider.c regmap_write(common->regmap, div_hw->reg, div_hw 76 drivers/clk/actions/owl-divider.c reg | (val << div_hw->shift)); div_hw 86 drivers/clk/actions/owl-divider.c return owl_divider_helper_set_rate(&div->common, &div->div_hw, div_hw 25 drivers/clk/actions/owl-divider.h struct owl_divider_hw div_hw; div_hw 41 drivers/clk/actions/owl-divider.h .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \ div_hw 60 drivers/clk/actions/owl-divider.h const struct owl_divider_hw *div_hw, div_hw 65 drivers/clk/actions/owl-divider.h const struct owl_divider_hw *div_hw, div_hw 69 drivers/clk/actions/owl-divider.h const struct owl_divider_hw *div_hw, div_hw 351 drivers/clk/clk-stm32h7.c struct clk_hw *div_hw; div_hw 368 drivers/clk/clk-stm32h7.c struct clk_hw *div_hw; div_hw 372 drivers/clk/clk-stm32h7.c mux_hw = div_hw = gate_hw = NULL; div_hw 394 drivers/clk/clk-stm32h7.c div_hw = &div->hw; div_hw 415 drivers/clk/clk-stm32h7.c composite->div_hw = div_hw; div_hw 1327 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_hw 1350 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_hw 1365 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_hw 1379 drivers/clk/clk-stm32h7.c c_cfg.div_hw, c_cfg.div_ops, div_hw 616 drivers/clk/clk-stm32mp1.c struct clk_hw *mux_hw, *div_hw, *gate_hw; div_hw 619 drivers/clk/clk-stm32mp1.c div_hw = NULL; div_hw 637 drivers/clk/clk-stm32mp1.c div_hw = _get_stm32_div(base, cfg->div, lock); div_hw 639 drivers/clk/clk-stm32mp1.c if (!IS_ERR(div_hw)) { div_hw 659 drivers/clk/clk-stm32mp1.c mux_hw, mux_ops, div_hw, div_ops, div_hw 132 drivers/clk/imx/clk-composite-8m.c struct clk_hw *div_hw, *gate_hw; div_hw 151 drivers/clk/imx/clk-composite-8m.c div_hw = &div->hw; div_hw 168 drivers/clk/imx/clk-composite-8m.c mux_hw, &clk_mux_ops, div_hw, div_hw 156 drivers/clk/mediatek/clk-mtk.c struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; div_hw 212 drivers/clk/mediatek/clk-mtk.c div_hw = &div->hw; div_hw 218 drivers/clk/mediatek/clk-mtk.c div_hw, div_ops, div_hw 211 drivers/clk/nxp/clk-lpc18xx-ccu.c struct clk_hw *div_hw = NULL; div_hw 223 drivers/clk/nxp/clk-lpc18xx-ccu.c div_hw = &div->hw; div_hw 232 drivers/clk/nxp/clk-lpc18xx-ccu.c div_hw, div_ops, div_hw 1434 drivers/clk/nxp/clk-lpc32xx.c struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; div_hw 1447 drivers/clk/nxp/clk-lpc32xx.c div_hw = &div0->clk.hw; div_hw 1456 drivers/clk/nxp/clk-lpc32xx.c mux_hw, mops, div_hw, dops, div_hw 40 drivers/clk/tegra/clk-periph.c struct clk_hw *div_hw = &periph->divider.hw; div_hw 42 drivers/clk/tegra/clk-periph.c __clk_hw_set_clk(div_hw, hw); div_hw 44 drivers/clk/tegra/clk-periph.c return div_ops->recalc_rate(div_hw, parent_rate); div_hw 52 drivers/clk/tegra/clk-periph.c struct clk_hw *div_hw = &periph->divider.hw; div_hw 54 drivers/clk/tegra/clk-periph.c __clk_hw_set_clk(div_hw, hw); div_hw 56 drivers/clk/tegra/clk-periph.c return div_ops->round_rate(div_hw, rate, prate); div_hw 64 drivers/clk/tegra/clk-periph.c struct clk_hw *div_hw = &periph->divider.hw; div_hw 66 drivers/clk/tegra/clk-periph.c __clk_hw_set_clk(div_hw, hw); div_hw 68 drivers/clk/tegra/clk-periph.c return div_ops->set_rate(div_hw, rate, parent_rate); div_hw 122 drivers/clk/tegra/clk-super.c struct clk_hw *div_hw = &super->frac_div.hw; div_hw 124 drivers/clk/tegra/clk-super.c __clk_hw_set_clk(div_hw, hw); div_hw 126 drivers/clk/tegra/clk-super.c return super->div_ops->round_rate(div_hw, rate, parent_rate); div_hw 133 drivers/clk/tegra/clk-super.c struct clk_hw *div_hw = &super->frac_div.hw; div_hw 135 drivers/clk/tegra/clk-super.c __clk_hw_set_clk(div_hw, hw); div_hw 137 drivers/clk/tegra/clk-super.c return super->div_ops->recalc_rate(div_hw, parent_rate); div_hw 144 drivers/clk/tegra/clk-super.c struct clk_hw *div_hw = &super->frac_div.hw; div_hw 146 drivers/clk/tegra/clk-super.c __clk_hw_set_clk(div_hw, hw); div_hw 148 drivers/clk/tegra/clk-super.c return super->div_ops->set_rate(div_hw, rate, parent_rate);