div_frc 143 drivers/clk/clk-versaclock5.c u32 div_frc; div_frc 406 drivers/clk/clk-versaclock5.c u32 div_int, div_frc; div_frc 412 drivers/clk/clk-versaclock5.c div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; div_frc 415 drivers/clk/clk-versaclock5.c return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); div_frc 423 drivers/clk/clk-versaclock5.c u64 div_frc; div_frc 436 drivers/clk/clk-versaclock5.c div_frc = rate % *parent_rate; div_frc 437 drivers/clk/clk-versaclock5.c div_frc *= BIT(24) - 1; div_frc 438 drivers/clk/clk-versaclock5.c do_div(div_frc, *parent_rate); div_frc 441 drivers/clk/clk-versaclock5.c hwdata->div_frc = (u32)div_frc; div_frc 443 drivers/clk/clk-versaclock5.c return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); div_frc 455 drivers/clk/clk-versaclock5.c fb[2] = hwdata->div_frc >> 16; div_frc 456 drivers/clk/clk-versaclock5.c fb[3] = hwdata->div_frc >> 8; div_frc 457 drivers/clk/clk-versaclock5.c fb[4] = hwdata->div_frc; div_frc 475 drivers/clk/clk-versaclock5.c u32 div_int, div_frc; div_frc 485 drivers/clk/clk-versaclock5.c div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | div_frc 489 drivers/clk/clk-versaclock5.c if (div_int == 0 && div_frc == 0) div_frc 493 drivers/clk/clk-versaclock5.c return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); div_frc 503 drivers/clk/clk-versaclock5.c u64 div_frc; div_frc 518 drivers/clk/clk-versaclock5.c div_frc = f_in % rate; div_frc 519 drivers/clk/clk-versaclock5.c div_frc <<= 24; div_frc 520 drivers/clk/clk-versaclock5.c do_div(div_frc, rate); div_frc 523 drivers/clk/clk-versaclock5.c hwdata->div_frc = (u32)div_frc; div_frc 525 drivers/clk/clk-versaclock5.c return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); div_frc 534 drivers/clk/clk-versaclock5.c hwdata->div_frc >> 22, hwdata->div_frc >> 14, div_frc 535 drivers/clk/clk-versaclock5.c hwdata->div_frc >> 6, hwdata->div_frc << 2,