div_frac_start     88 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	u32 div_frac_start;
div_frac_start    305 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	u32 duration, div_frac_start;
div_frac_start    312 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
div_frac_start    317 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pout->div_frac_start = div_frac_start;
div_frac_start    533 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	data = pout->div_frac_start & 0xff;
div_frac_start    535 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	data = (pout->div_frac_start >> 8) & 0xff;
div_frac_start    537 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	data = (pout->div_frac_start >> 16) & 0xf;
div_frac_start    631 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	u32 div_frac_start;
div_frac_start    640 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
div_frac_start    642 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
div_frac_start    644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
div_frac_start    647 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("div_frac_start = %x", div_frac_start);
div_frac_start    651 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	vco_rate += ((ref_clk * div_frac_start) / multiplier);