div_fbx1000       134 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	unsigned long div_fbx1000, gen_vco_clk;
div_fbx1000       165 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
div_fbx1000       166 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
div_fbx1000       170 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
div_fbx1000       171 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
div_fbx1000       176 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	rem = div_fbx1000 % 1000;
div_fbx1000       179 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	DBG("div_fb = %lu", div_fbx1000);
div_fbx1000       190 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));
div_fbx1000       196 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));