div6_clks         121 arch/sh/kernel/cpu/sh4a/clock-sh7343.c struct clk div6_clks[DIV6_NR] = {
div6_clks         203 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
div6_clks         271 arch/sh/kernel/cpu/sh4a/clock-sh7343.c 		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
div6_clks         124 arch/sh/kernel/cpu/sh4a/clock-sh7366.c struct clk div6_clks[DIV6_NR] = {
div6_clks         201 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
div6_clks         264 arch/sh/kernel/cpu/sh4a/clock-sh7366.c 		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
div6_clks         137 arch/sh/kernel/cpu/sh4a/clock-sh7722.c struct clk div6_clks[DIV6_NR] = {
div6_clks         188 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
div6_clks         247 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
div6_clks         137 arch/sh/kernel/cpu/sh4a/clock-sh7723.c struct clk div6_clks[DIV6_NR] = {
div6_clks         213 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
div6_clks         295 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
div6_clks         189 arch/sh/kernel/cpu/sh4a/clock-sh7724.c static struct clk div6_clks[DIV6_NR] = {
div6_clks         275 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
div6_clks         276 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
div6_clks         277 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
div6_clks         278 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
div6_clks         279 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
div6_clks         361 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 		ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);