div4_clks 81 arch/sh/kernel/cpu/sh2a/clock-sh7264.c struct clk div4_clks[DIV4_NR] = { div4_clks 93 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */ div4_clks 94 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */ div4_clks 95 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */ div4_clks 96 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */ div4_clks 97 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */ div4_clks 98 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */ div4_clks 99 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */ div4_clks 100 arch/sh/kernel/cpu/sh2a/clock-sh7264.c [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */ div4_clks 111 arch/sh/kernel/cpu/sh2a/clock-sh7264.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 112 arch/sh/kernel/cpu/sh2a/clock-sh7264.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 151 arch/sh/kernel/cpu/sh2a/clock-sh7264.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 109 arch/sh/kernel/cpu/sh2a/clock-sh7269.c struct clk div4_clks[DIV4_NR] = { div4_clks 146 arch/sh/kernel/cpu/sh2a/clock-sh7269.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 147 arch/sh/kernel/cpu/sh2a/clock-sh7269.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 175 arch/sh/kernel/cpu/sh2a/clock-sh7269.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 108 arch/sh/kernel/cpu/sh4a/clock-sh7343.c struct clk div4_clks[DIV4_NR] = { div4_clks 139 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), div4_clks 140 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), div4_clks 141 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), div4_clks 142 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), div4_clks 143 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), div4_clks 144 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), div4_clks 145 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), div4_clks 146 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), div4_clks 147 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), div4_clks 148 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), div4_clks 149 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), div4_clks 150 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 153 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), div4_clks 154 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 155 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 156 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), div4_clks 157 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), div4_clks 158 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), div4_clks 159 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), div4_clks 160 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), div4_clks 161 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), div4_clks 163 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 164 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0), div4_clks 166 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), div4_clks 167 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), div4_clks 168 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), div4_clks 169 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), div4_clks 170 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), div4_clks 172 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), div4_clks 173 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), div4_clks 174 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), div4_clks 175 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), div4_clks 176 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), div4_clks 177 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), div4_clks 178 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), div4_clks 179 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), div4_clks 180 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), div4_clks 181 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), div4_clks 182 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), div4_clks 193 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 194 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), div4_clks 195 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 196 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 197 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), div4_clks 198 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 199 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), div4_clks 200 arch/sh/kernel/cpu/sh4a/clock-sh7343.c CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), div4_clks 268 arch/sh/kernel/cpu/sh4a/clock-sh7343.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 111 arch/sh/kernel/cpu/sh4a/clock-sh7366.c struct clk div4_clks[DIV4_NR] = { div4_clks 142 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), div4_clks 143 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), div4_clks 144 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), div4_clks 145 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), div4_clks 146 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), div4_clks 147 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), div4_clks 148 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), div4_clks 149 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), div4_clks 150 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), div4_clks 151 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), div4_clks 152 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), div4_clks 153 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 156 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), div4_clks 157 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 158 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 159 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), div4_clks 160 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), div4_clks 161 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), div4_clks 162 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), div4_clks 164 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 166 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), div4_clks 167 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), div4_clks 168 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), div4_clks 169 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), div4_clks 170 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), div4_clks 171 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), div4_clks 172 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), div4_clks 173 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), div4_clks 174 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), div4_clks 175 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), div4_clks 176 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), div4_clks 177 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), div4_clks 178 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), div4_clks 179 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), div4_clks 180 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), div4_clks 191 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 192 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), div4_clks 193 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 194 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 195 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), div4_clks 196 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 197 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), div4_clks 198 arch/sh/kernel/cpu/sh4a/clock-sh7366.c CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), div4_clks 261 arch/sh/kernel/cpu/sh4a/clock-sh7366.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 113 arch/sh/kernel/cpu/sh4a/clock-sh7722.c struct clk div4_clks[DIV4_NR] = { div4_clks 142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), div4_clks 143 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), div4_clks 144 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 147 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 148 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 149 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0), div4_clks 150 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), div4_clks 152 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 155 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0), div4_clks 157 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0), div4_clks 158 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), div4_clks 159 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), div4_clks 160 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), div4_clks 161 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), div4_clks 162 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), div4_clks 163 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), div4_clks 164 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), div4_clks 165 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), div4_clks 166 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0), div4_clks 177 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 178 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), div4_clks 179 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 180 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 181 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), div4_clks 182 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 236 arch/sh/kernel/cpu/sh4a/clock-sh7722.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 114 arch/sh/kernel/cpu/sh4a/clock-sh7723.c struct clk div4_clks[DIV4_NR] = { div4_clks 143 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), div4_clks 144 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), div4_clks 145 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), div4_clks 146 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), div4_clks 147 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), div4_clks 148 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), div4_clks 149 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT), div4_clks 150 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), div4_clks 151 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), div4_clks 152 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), div4_clks 153 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), div4_clks 154 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 157 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), div4_clks 158 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), div4_clks 159 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 160 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 161 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 162 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 163 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), div4_clks 164 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), div4_clks 165 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), div4_clks 166 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), div4_clks 167 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), div4_clks 168 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0), div4_clks 170 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 173 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), div4_clks 174 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0), div4_clks 175 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), div4_clks 176 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), div4_clks 177 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), div4_clks 178 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), div4_clks 179 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), div4_clks 180 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), div4_clks 182 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0), div4_clks 183 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0), div4_clks 184 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), div4_clks 185 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), div4_clks 186 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), div4_clks 187 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), div4_clks 188 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), div4_clks 189 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), div4_clks 190 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), div4_clks 191 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), div4_clks 202 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 203 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), div4_clks 204 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 205 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 206 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), div4_clks 207 arch/sh/kernel/cpu/sh4a/clock-sh7723.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 284 arch/sh/kernel/cpu/sh4a/clock-sh7723.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 153 arch/sh/kernel/cpu/sh4a/clock-sh7724.c struct clk div4_clks[DIV4_NR] = { div4_clks 203 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), div4_clks 204 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), div4_clks 205 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), div4_clks 206 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), div4_clks 207 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), div4_clks 208 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), div4_clks 209 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), div4_clks 210 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), div4_clks 211 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), div4_clks 212 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), div4_clks 213 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), div4_clks 214 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), div4_clks 215 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 218 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), div4_clks 219 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 220 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 221 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 222 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 223 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), div4_clks 224 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), div4_clks 225 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), div4_clks 226 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), div4_clks 227 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), div4_clks 231 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 232 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), div4_clks 234 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), div4_clks 235 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), div4_clks 236 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), div4_clks 237 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), div4_clks 238 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), div4_clks 239 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), div4_clks 240 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), div4_clks 241 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), div4_clks 242 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), div4_clks 243 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), div4_clks 244 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), div4_clks 245 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), div4_clks 246 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), div4_clks 247 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), div4_clks 248 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), div4_clks 249 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), div4_clks 250 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), div4_clks 251 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), div4_clks 252 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), div4_clks 253 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), div4_clks 254 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), div4_clks 255 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), div4_clks 256 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), div4_clks 268 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 269 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 270 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 271 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 272 arch/sh/kernel/cpu/sh4a/clock-sh7724.c CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), div4_clks 358 arch/sh/kernel/cpu/sh4a/clock-sh7724.c ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); div4_clks 72 arch/sh/kernel/cpu/sh4a/clock-sh7734.c struct clk div4_clks[DIV4_NR] = { div4_clks 126 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), div4_clks 127 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), div4_clks 128 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), div4_clks 129 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), div4_clks 130 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), div4_clks 131 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), div4_clks 132 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), div4_clks 133 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), div4_clks 134 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), div4_clks 135 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), div4_clks 136 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 137 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), div4_clks 138 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), div4_clks 139 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), div4_clks 140 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 141 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 142 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 143 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), div4_clks 146 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), div4_clks 147 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), div4_clks 148 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), div4_clks 149 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), div4_clks 150 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), div4_clks 151 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0), div4_clks 152 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0), div4_clks 153 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), div4_clks 154 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), div4_clks 157 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0), div4_clks 158 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0), div4_clks 159 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), div4_clks 160 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), div4_clks 161 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), div4_clks 162 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), div4_clks 163 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0), div4_clks 164 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0), div4_clks 165 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0), div4_clks 166 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0), div4_clks 167 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0), div4_clks 168 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0), div4_clks 169 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0), div4_clks 170 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0), div4_clks 171 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0), div4_clks 172 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0), div4_clks 173 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0), div4_clks 174 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0), div4_clks 175 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0), div4_clks 184 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 185 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), div4_clks 186 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]), div4_clks 187 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 188 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]), div4_clks 189 arch/sh/kernel/cpu/sh4a/clock-sh7734.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 249 arch/sh/kernel/cpu/sh4a/clock-sh7734.c ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), div4_clks 65 arch/sh/kernel/cpu/sh4a/clock-sh7757.c struct clk div4_clks[DIV4_NR] = { div4_clks 85 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), div4_clks 86 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), div4_clks 89 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0), div4_clks 90 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), div4_clks 91 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), div4_clks 92 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), div4_clks 93 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), div4_clks 94 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), div4_clks 95 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), div4_clks 96 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), div4_clks 99 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), div4_clks 108 arch/sh/kernel/cpu/sh4a/clock-sh7757.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 109 arch/sh/kernel/cpu/sh4a/clock-sh7757.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 110 arch/sh/kernel/cpu/sh4a/clock-sh7757.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 145 arch/sh/kernel/cpu/sh4a/clock-sh7757.c ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), div4_clks 69 arch/sh/kernel/cpu/sh4a/clock-sh7785.c struct clk div4_clks[DIV4_NR] = { div4_clks 91 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), div4_clks 92 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), div4_clks 93 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), div4_clks 94 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), div4_clks 95 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), div4_clks 96 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), div4_clks 97 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), div4_clks 98 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), div4_clks 99 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), div4_clks 100 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), div4_clks 101 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), div4_clks 102 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), div4_clks 103 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 104 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 105 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), div4_clks 106 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), div4_clks 122 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 123 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), div4_clks 124 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), div4_clks 125 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), div4_clks 126 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 127 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 128 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), div4_clks 129 arch/sh/kernel/cpu/sh4a/clock-sh7785.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 168 arch/sh/kernel/cpu/sh4a/clock-sh7785.c ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), div4_clks 70 arch/sh/kernel/cpu/sh4a/clock-sh7786.c struct clk div4_clks[DIV4_NR] = { div4_clks 92 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), div4_clks 93 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), div4_clks 94 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), div4_clks 95 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), div4_clks 96 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), div4_clks 97 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), div4_clks 98 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), div4_clks 99 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), div4_clks 100 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), div4_clks 101 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), div4_clks 102 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), div4_clks 103 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), div4_clks 104 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), div4_clks 105 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), div4_clks 106 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), div4_clks 107 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), div4_clks 108 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 109 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 110 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), div4_clks 111 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), div4_clks 112 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), div4_clks 131 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 132 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), div4_clks 133 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), div4_clks 134 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 135 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 136 arch/sh/kernel/cpu/sh4a/clock-sh7786.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 183 arch/sh/kernel/cpu/sh4a/clock-sh7786.c ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), div4_clks 64 arch/sh/kernel/cpu/sh4a/clock-shx3.c struct clk div4_clks[DIV4_NR] = { div4_clks 83 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), div4_clks 84 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), div4_clks 85 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), div4_clks 86 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), div4_clks 87 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), div4_clks 88 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), div4_clks 89 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), div4_clks 90 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), div4_clks 91 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0), div4_clks 92 arch/sh/kernel/cpu/sh4a/clock-shx3.c [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), div4_clks 106 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), div4_clks 107 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]), div4_clks 108 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), div4_clks 109 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), div4_clks 110 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), div4_clks 111 arch/sh/kernel/cpu/sh4a/clock-shx3.c CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), div4_clks 142 arch/sh/kernel/cpu/sh4a/clock-shx3.c ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), div4_clks 42 drivers/clk/renesas/clk-r8a73a4.c static struct div4_clk div4_clks[] = { div4_clks 166 drivers/clk/renesas/clk-r8a73a4.c for (c = div4_clks; c->name; c++) { div4_clks 39 drivers/clk/renesas/clk-r8a7740.c static struct div4_clk div4_clks[] = { div4_clks 122 drivers/clk/renesas/clk-r8a7740.c for (c = div4_clks; c->name; c++) { div4_clks 47 drivers/clk/renesas/clk-sh73a0.c static const struct div4_clk div4_clks[] = { div4_clks 138 drivers/clk/renesas/clk-sh73a0.c for (c = div4_clks; c->name; c++) {