div1 372 arch/mips/alchemy/common/clock.c long div1, div2; div1 374 arch/mips/alchemy/common/clock.c div1 = prate / rate; div1 375 arch/mips/alchemy/common/clock.c if ((prate / div1) > rate) div1 376 arch/mips/alchemy/common/clock.c div1++; div1 379 arch/mips/alchemy/common/clock.c if (div1 & 1) div1 380 arch/mips/alchemy/common/clock.c div1++; /* stay <=prate */ div1 383 arch/mips/alchemy/common/clock.c div2 = (div1 / scale) - 1; /* value to write to register */ div1 390 arch/mips/alchemy/common/clock.c div1 = ((div2 + 1) * scale); div1 391 arch/mips/alchemy/common/clock.c return div1; div1 456 drivers/clk/clk-vt8500.c int div1, div2; div1 462 drivers/clk/clk-vt8500.c for (div1 = 1; div1 >= 0; div1--) div1 465 drivers/clk/clk-vt8500.c tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); div1 471 drivers/clk/clk-vt8500.c *filter = wm8750_get_filter(parent_rate, div1); div1 473 drivers/clk/clk-vt8500.c *divisor1 = div1; div1 481 drivers/clk/clk-vt8500.c *divisor1 = div1; div1 504 drivers/clk/clk-vt8500.c int div1, div2; div1 510 drivers/clk/clk-vt8500.c for (div1 = 1; div1 >= 0; div1--) div1 514 drivers/clk/clk-vt8500.c ((div1 + 1) * (1 << div2)); div1 521 drivers/clk/clk-vt8500.c *divisor1 = div1; div1 529 drivers/clk/clk-vt8500.c *divisor1 = div1; div1 550 drivers/clk/clk-vt8500.c u32 filter, mul, div1, div2; div1 559 drivers/clk/clk-vt8500.c ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1); div1 561 drivers/clk/clk-vt8500.c pll_val = VT8500_BITS_TO_VAL(mul, div1); div1 564 drivers/clk/clk-vt8500.c ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); div1 566 drivers/clk/clk-vt8500.c pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); div1 569 drivers/clk/clk-vt8500.c ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); div1 571 drivers/clk/clk-vt8500.c pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); div1 574 drivers/clk/clk-vt8500.c ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); div1 576 drivers/clk/clk-vt8500.c pll_val = WM8850_BITS_TO_VAL(mul, div1, div2); div1 601 drivers/clk/clk-vt8500.c u32 filter, mul, div1, div2; div1 607 drivers/clk/clk-vt8500.c ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1); div1 609 drivers/clk/clk-vt8500.c round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); div1 612 drivers/clk/clk-vt8500.c ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); div1 614 drivers/clk/clk-vt8500.c round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); div1 617 drivers/clk/clk-vt8500.c ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); div1 619 drivers/clk/clk-vt8500.c round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); div1 622 drivers/clk/clk-vt8500.c ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2); div1 624 drivers/clk/clk-vt8500.c round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); div1 52 drivers/clk/imx/clk-composite-8m.c int div1, div2; div1 59 drivers/clk/imx/clk-composite-8m.c for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { div1 61 drivers/clk/imx/clk-composite-8m.c int new_error = ((parent_rate / div1) / div2) - rate; div1 64 drivers/clk/imx/clk-composite-8m.c *prediv = div1; div1 155 drivers/clk/samsung/clk-cpu.c unsigned long div0, div1 = 0, mux_reg; div1 174 drivers/clk/samsung/clk-cpu.c div1 = cfg_data->div1; div1 176 drivers/clk/samsung/clk-cpu.c div1 = readl(base + E4210_DIV_CPU1) & div1 216 drivers/clk/samsung/clk-cpu.c writel(div1, base + E4210_DIV_CPU1); div1 283 drivers/clk/samsung/clk-cpu.c unsigned long div0, div1 = 0, mux_reg; div1 300 drivers/clk/samsung/clk-cpu.c div1 = cfg_data->div1; div1 329 drivers/clk/samsung/clk-cpu.c writel(div1, base + E5433_DIV_CPU1); div1 28 drivers/clk/samsung/clk-cpu.h unsigned long div1; div1 110 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ div1 112 drivers/clk/uniphier/clk-uniphier.h UNIPHIER_CLK_DIV(parent, div1) div1 114 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ div1 115 drivers/clk/uniphier/clk-uniphier.h UNIPHIER_CLK_DIV2(parent, div0, div1), \ div1 118 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ div1 119 drivers/clk/uniphier/clk-uniphier.h UNIPHIER_CLK_DIV2(parent, div0, div1), \ div1 1411 drivers/gpu/drm/i915/display/intel_ddi.c u32 m1, m2_int, m2_frac, div1, div2, ref_clock; div1 1425 drivers/gpu/drm/i915/display/intel_ddi.c div1 = 2; div1 1428 drivers/gpu/drm/i915/display/intel_ddi.c div1 = 3; div1 1431 drivers/gpu/drm/i915/display/intel_ddi.c div1 = 5; div1 1434 drivers/gpu/drm/i915/display/intel_ddi.c div1 = 7; div1 1455 drivers/gpu/drm/i915/display/intel_ddi.c tmp = div_u64(tmp, 5 * div1 * div2); div1 2636 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int div1 = div1_vals[i]; div1 2639 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int dco = div1 * div2 * clock_khz * 5; div1 2655 drivers/gpu/drm/i915/display/intel_dpll_mgr.c switch (div1) { div1 2657 drivers/gpu/drm/i915/display/intel_dpll_mgr.c MISSING_CASE(div1); div1 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 div1 = sor->asy.link == 3; div1 132 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); div1 799 drivers/i2c/busses/i2c-s3c2410.c unsigned int *div1, unsigned int *divs) div1 818 drivers/i2c/busses/i2c-s3c2410.c *div1 = calc_div1; div1 832 drivers/i2c/busses/i2c-s3c2410.c unsigned int divs, div1; div1 846 drivers/i2c/busses/i2c-s3c2410.c freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); div1 861 drivers/i2c/busses/i2c-s3c2410.c if (div1 == 512) div1 334 drivers/i2c/busses/i2c-sprd.c u32 div1 = I2C_ADDR_DVD1_CALC(high, low); div1 337 drivers/i2c/busses/i2c-sprd.c writel(div1, i2c_dev->base + ADDR_DVD1); div1 1274 drivers/media/dvb-frontends/stb0899_algo.c int div1, div2, rem1, rem2; div1 1276 drivers/media/dvb-frontends/stb0899_algo.c div1 = config->btr_nco_bits / 2; div1 1277 drivers/media/dvb-frontends/stb0899_algo.c div2 = config->btr_nco_bits - div1 - 1; div1 1285 drivers/media/dvb-frontends/stb0899_algo.c intval1 = internal->master_clk / (1 << div1); div1 1288 drivers/media/dvb-frontends/stb0899_algo.c rem1 = internal->master_clk % (1 << div1); div1 1291 drivers/media/dvb-frontends/stb0899_algo.c srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); div1 196 drivers/media/tuners/mt2060.c u32 div1,num1,div2,num2; div1 228 drivers/media/tuners/mt2060.c div1 = num1 / 64; div1 249 drivers/media/tuners/mt2060.c b[2] = div1; div1 256 drivers/media/tuners/mt2060.c dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); div1 89 drivers/media/tuners/mt2131.c u32 div1, num1, div2, num2; div1 106 drivers/media/tuners/mt2131.c div1 = num1 / 8192; div1 137 drivers/media/tuners/mt2131.c b[3] = div1; div1 146 drivers/media/tuners/mt2131.c (int)div1, (int)num1, (int)div2, (int)num2); div1 317 drivers/spi/spi-omap-uwire.c int div1; div1 362 drivers/spi/spi-omap-uwire.c div1 = 2; div1 365 drivers/spi/spi-omap-uwire.c div1 = 4; div1 368 drivers/spi/spi-omap-uwire.c div1 = 7; div1 372 drivers/spi/spi-omap-uwire.c div1 = 10; div1 375 drivers/spi/spi-omap-uwire.c div2 = (rate / div1 + hz - 1) / hz; div1 392 drivers/spi/spi-omap-uwire.c rate /= div1; div1 533 drivers/staging/comedi/drivers/adl_pci9118.c unsigned int *div1, unsigned int *div2, div1 539 drivers/staging/comedi/drivers/adl_pci9118.c *div1 = *tim2 / pacer->osc_base; /* convert timer (burst) */ div1 541 drivers/staging/comedi/drivers/adl_pci9118.c *div2 = *div2 / *div1; /* major timer is c1*c2 */ div1 545 drivers/staging/comedi/drivers/adl_pci9118.c *tim2 = *div1 * pacer->osc_base; /* real convert timer */ div1 553 drivers/staging/comedi/drivers/adl_pci9118.c *tim1 = *div1 * *div2 * pacer->osc_base; div1 214 sound/soc/codecs/da7210.c u8 div1; div1 1002 sound/soc/codecs/da7210.c pll_div1 = da7210_pll_div[cnt].div1;