display_v_start    87 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 display_v_start, display_v_end;
display_v_start   103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
display_v_start   109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
display_v_start   125 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		active_v_start = display_v_start;
display_v_start   174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
display_v_start    45 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_start    66 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew;
display_v_start    77 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start);
display_v_start    91 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_start   116 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
display_v_start   127 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
display_v_start   262 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_start   287 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + lcdc_hsync_skew;
display_v_start   298 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start);
display_v_start   103 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_start   152 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
display_v_start   161 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 		display_v_start += mode->htotal - mode->hsync_start;
display_v_start   175 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);