display_v_end      87 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 display_v_start, display_v_end;
display_v_end     105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
display_v_end     110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		display_v_end -= p->h_front_porch;
display_v_end     175 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
display_v_end      45 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_end      67 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_skew - 1;
display_v_end      78 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end);
display_v_end      91 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_end     117 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
display_v_end     128 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
display_v_end     262 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_end     288 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_skew - 1;
display_v_end     299 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end);
display_v_end     103 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t display_v_start, display_v_end;
display_v_end     153 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
display_v_end     162 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 		display_v_end -= mode->hsync_start - mode->hdisplay;
display_v_end     176 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);