display_config    584 arch/arm/mach-davinci/da850.c 						*display_config)
display_config    586 arch/arm/mach-davinci/da850.c 	da850_vpif_display_dev.dev.platform_data = display_config;
display_config    609 arch/arm/mach-davinci/dm646x.c void dm646x_setup_vpif(struct vpif_display_config *display_config,
display_config    627 arch/arm/mach-davinci/dm646x.c 	vpif_display_dev.dev.platform_data = display_config;
display_config    124 arch/arm/mach-davinci/include/mach/da8xx.h 			(struct vpif_display_config *display_config);
display_config     57 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->display_config = &adev->pm.pm_display_cfg;
display_config   1036 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	const struct amd_pp_display_configuration *display_config)
display_config   1044 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	phm_store_dal_configuration_data(hwmgr, display_config);
display_config    869 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu->display_config = &adev->pm.pm_display_cfg;
display_config   1403 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 				     const struct amd_pp_display_configuration *display_config)
display_config   1411 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	if (!display_config)
display_config   1417 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 				   display_config->min_dcef_deep_sleep_set_clk / 100);
display_config   1419 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	for (index = 0; index < display_config->num_path_including_non_display; index++) {
display_config   1420 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		if (display_config->displays[index].controller_id != 0)
display_config   1426 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
display_config   1427 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			   display_config->cpu_cc6_disable,
display_config   1428 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			   display_config->cpu_pstate_disable,
display_config   1429 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			   display_config->nb_pstate_switch_disable);
display_config    288 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		    const struct amd_pp_display_configuration *display_config)
display_config    295 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (display_config == NULL)
display_config    299 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
display_config    301 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	for (index = 0; index < display_config->num_path_including_non_display; index++) {
display_config    302 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		if (display_config->displays[index].controller_id != 0)
display_config    316 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 				display_config->cpu_pstate_separation_time,
display_config    317 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 				display_config->cpu_cc6_disable,
display_config    318 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 				display_config->cpu_pstate_disable,
display_config    319 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 				display_config->nb_pstate_switch_disable);
display_config    198 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
display_config    571 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
display_config    572 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
display_config    664 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						hwmgr->display_config->num_display > 3 ?
display_config   2924 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
display_config   2925 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
display_config   2956 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->display_config->num_display == 0)
display_config   2959 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
display_config   2960 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					  !hwmgr->display_config->multi_monitor_in_sync) ||
display_config   2962 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
display_config   3640 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
display_config   4051 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->display_config->num_display > 1 &&
display_config   4052 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			!hwmgr->display_config->multi_monitor_in_sync)
display_config   4073 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
display_config   4077 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	refresh_rate = hwmgr->display_config->vrefresh;
display_config   4084 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
display_config   4170 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
display_config   4173 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
display_config   4177 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
display_config   4179 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
display_config    700 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clock = hwmgr->display_config->min_core_set_clock;
display_config    755 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
display_config   1053 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
display_config   1054 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->display_config->min_mem_set_clock :
display_config   1062 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			|| (hwmgr->display_config->num_display >= 3);
display_config   3179 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
display_config   3180 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
display_config   3220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->display_config->num_display == 0)
display_config   3223 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
display_config   3224 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					  !hwmgr->display_config->multi_monitor_in_sync) ||
display_config   3256 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
display_config   3322 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
display_config   3924 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if ((hwmgr->display_config->num_display > 1) &&
display_config   3925 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	     !hwmgr->display_config->multi_monitor_in_sync &&
display_config   3926 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	     !hwmgr->display_config->nb_pstate_switch_disable)
display_config   3931 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
display_config   3932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
display_config   3933 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
display_config   4597 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
display_config   4684 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
display_config   4688 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
display_config   1479 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if ((hwmgr->display_config->num_display > 1) &&
display_config   1480 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	     !hwmgr->display_config->multi_monitor_in_sync &&
display_config   1481 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	     !hwmgr->display_config->nb_pstate_switch_disable)
display_config   1486 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
display_config   1487 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
display_config   1488 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
display_config   2179 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
display_config   2180 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			          !hwmgr->display_config->multi_monitor_in_sync) ||
display_config   2182 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
display_config   2233 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
display_config   2234 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
display_config   2241 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
display_config   2249 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable)
display_config   2388 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
display_config   2438 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
display_config   2442 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
display_config   2300 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
display_config   2301 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
display_config   2302 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
display_config   3564 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			hwmgr->display_config->num_display);
display_config   3638 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
display_config   3639 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c                            !hwmgr->display_config->multi_monitor_in_sync) ||
display_config   3641 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
display_config   3692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
display_config   3693 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
display_config   3700 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
display_config   3708 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable)
display_config   3713 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	     hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
display_config   3724 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
display_config   3813 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			hwmgr->display_config->num_display)
display_config   3818 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	    hwmgr->display_config->min_core_set_clock_in_sr))
display_config    355 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	struct amd_pp_display_configuration  *display_config;
display_config    807 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 					    *display_config);
display_config    431 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 		const struct amd_pp_display_configuration *display_config);
display_config    783 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	const struct amd_pp_display_configuration *display_config;
display_config    882 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 						  smu->display_config->num_display);
display_config   1259 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
display_config   1260 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
display_config   1261 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
display_config   1234 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1235 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config    978 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
display_config    982 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
display_config   1203 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1204 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config    932 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			hwmgr->display_config->min_core_set_clock_in_sr;
display_config   1282 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1283 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config    944 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
display_config    948 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
display_config   1106 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1107 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config    659 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			hwmgr->display_config->min_core_set_clock_in_sr;
display_config   1016 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1017 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config    836 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
display_config    840 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
display_config   1010 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
display_config   1011 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
display_config   2097 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					    smu->display_config->num_display);
display_config   2112 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	disable_mclk_switching = ((1 < smu->display_config->num_display) &&
display_config   2113 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				  !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
display_config   2114 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
display_config   2161 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
display_config   2162 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
display_config   2169 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
display_config   2177 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (smu->display_config->nb_pstate_switch_disable)
display_config   2259 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
display_config   2260 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
display_config   2261 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;