dispctrl          400 drivers/gpu/drm/vc4/vc4_crtc.c 		u32 dispctrl;
dispctrl          418 drivers/gpu/drm/vc4/vc4_crtc.c 		dispctrl = HVS_READ(SCALER_DISPCTRL) &
dispctrl          420 drivers/gpu/drm/vc4/vc4_crtc.c 		HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
dispctrl          160 drivers/gpu/drm/vc4/vc4_hvs.c 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
dispctrl          162 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
dispctrl          164 drivers/gpu/drm/vc4/vc4_hvs.c 	HVS_WRITE(SCALER_DISPCTRL, dispctrl);
dispctrl          170 drivers/gpu/drm/vc4/vc4_hvs.c 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
dispctrl          172 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
dispctrl          176 drivers/gpu/drm/vc4/vc4_hvs.c 	HVS_WRITE(SCALER_DISPCTRL, dispctrl);
dispctrl          225 drivers/gpu/drm/vc4/vc4_hvs.c 	u32 dispctrl;
dispctrl          272 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl = HVS_READ(SCALER_DISPCTRL);
dispctrl          274 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl |= SCALER_DISPCTRL_ENABLE;
dispctrl          275 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
dispctrl          282 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
dispctrl          283 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
dispctrl          296 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
dispctrl          298 drivers/gpu/drm/vc4/vc4_hvs.c 	HVS_WRITE(SCALER_DISPCTRL, dispctrl);