dispc 35 drivers/gpu/drm/omapdrm/dss/base.c return dss->dispc; dispc 50 drivers/gpu/drm/omapdrm/dss/dispc.c #define REG_GET(dispc, idx, start, end) \ dispc 51 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_GET(dispc_read_reg(dispc, idx), start, end) dispc 53 drivers/gpu/drm/omapdrm/dss/dispc.c #define REG_FLD_MOD(dispc, idx, val, start, end) \ dispc 54 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, idx, \ dispc 55 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_MOD(dispc_read_reg(dispc, idx), val, start, end)) dispc 100 drivers/gpu/drm/omapdrm/dss/dispc.c int (*calc_scaling)(struct dispc_device *dispc, dispc 344 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_fclk_rate(struct dispc_device *dispc); dispc 345 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_core_clk_rate(struct dispc_device *dispc); dispc 346 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, dispc 348 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, dispc 351 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, dispc 353 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, dispc 356 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask); dispc 358 drivers/gpu/drm/omapdrm/dss/dispc.c static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) dispc 360 drivers/gpu/drm/omapdrm/dss/dispc.c __raw_writel(val, dispc->base + idx); dispc 363 drivers/gpu/drm/omapdrm/dss/dispc.c static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) dispc 365 drivers/gpu/drm/omapdrm/dss/dispc.c return __raw_readl(dispc->base + idx); dispc 368 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, dispc 373 drivers/gpu/drm/omapdrm/dss/dispc.c return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); dispc 376 drivers/gpu/drm/omapdrm/dss/dispc.c static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, dispc 384 drivers/gpu/drm/omapdrm/dss/dispc.c spin_lock_irqsave(&dispc->control_lock, flags); dispc 385 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); dispc 386 drivers/gpu/drm/omapdrm/dss/dispc.c spin_unlock_irqrestore(&dispc->control_lock, flags); dispc 388 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); dispc 392 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_get_num_ovls(struct dispc_device *dispc) dispc 394 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->feat->num_ovls; dispc 397 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_get_num_mgrs(struct dispc_device *dispc) dispc 399 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->feat->num_mgrs; dispc 402 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_get_reg_field(struct dispc_device *dispc, dispc 406 drivers/gpu/drm/omapdrm/dss/dispc.c if (id >= dispc->feat->num_reg_fields) dispc 409 drivers/gpu/drm/omapdrm/dss/dispc.c *start = dispc->feat->reg_fields[id].start; dispc 410 drivers/gpu/drm/omapdrm/dss/dispc.c *end = dispc->feat->reg_fields[id].end; dispc 413 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_has_feature(struct dispc_device *dispc, dispc 418 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc->feat->num_features; i++) { dispc 419 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->features[i] == id) dispc 426 drivers/gpu/drm/omapdrm/dss/dispc.c #define SR(dispc, reg) \ dispc 427 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg) dispc 428 drivers/gpu/drm/omapdrm/dss/dispc.c #define RR(dispc, reg) \ dispc 429 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)]) dispc 431 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_save_context(struct dispc_device *dispc) dispc 437 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, IRQENABLE); dispc 438 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL); dispc 439 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG); dispc 440 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, LINE_NUMBER); dispc 441 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || dispc 442 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) dispc 443 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, GLOBAL_ALPHA); dispc 444 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { dispc 445 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL2); dispc 446 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG2); dispc 448 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { dispc 449 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL3); dispc 450 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG3); dispc 453 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { dispc 454 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DEFAULT_COLOR(i)); dispc 455 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TRANS_COLOR(i)); dispc 456 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, SIZE_MGR(i)); dispc 459 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TIMING_H(i)); dispc 460 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TIMING_V(i)); dispc 461 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, POL_FREQ(i)); dispc 462 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DIVISORo(i)); dispc 464 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE1(i)); dispc 465 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE2(i)); dispc 466 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE3(i)); dispc 468 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CPR)) { dispc 469 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_R(i)); dispc 470 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_G(i)); dispc 471 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_B(i)); dispc 475 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); i++) { dispc 476 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA0(i)); dispc 477 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA1(i)); dispc 478 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_POSITION(i)); dispc 479 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_SIZE(i)); dispc 480 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ATTRIBUTES(i)); dispc 481 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIFO_THRESHOLD(i)); dispc 482 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ROW_INC(i)); dispc 483 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PIXEL_INC(i)); dispc 484 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_PRELOAD)) dispc 485 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PRELOAD(i)); dispc 487 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_WINDOW_SKIP(i)); dispc 488 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_TABLE_BA(i)); dispc 491 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR(i)); dispc 492 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PICTURE_SIZE(i)); dispc 493 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU0(i)); dispc 494 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU1(i)); dispc 497 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_H(i, j)); dispc 500 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_HV(i, j)); dispc 503 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_CONV_COEF(i, j)); dispc 505 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { dispc 507 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_V(i, j)); dispc 510 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { dispc 511 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA0_UV(i)); dispc 512 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA1_UV(i)); dispc 513 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR2(i)); dispc 514 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU2_0(i)); dispc 515 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU2_1(i)); dispc 518 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_H2(i, j)); dispc 521 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_HV2(i, j)); dispc 524 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_V2(i, j)); dispc 526 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ATTR2)) dispc 527 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ATTRIBUTES2(i)); dispc 530 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) dispc 531 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DIVISOR); dispc 533 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->ctx_valid = true; dispc 538 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_restore_context(struct dispc_device *dispc) dispc 544 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->ctx_valid) dispc 549 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG); dispc 550 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, LINE_NUMBER); dispc 551 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || dispc 552 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) dispc 553 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, GLOBAL_ALPHA); dispc 554 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 555 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG2); dispc 556 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) dispc 557 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONFIG3); dispc 559 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { dispc 560 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DEFAULT_COLOR(i)); dispc 561 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TRANS_COLOR(i)); dispc 562 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, SIZE_MGR(i)); dispc 565 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TIMING_H(i)); dispc 566 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, TIMING_V(i)); dispc 567 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, POL_FREQ(i)); dispc 568 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DIVISORo(i)); dispc 570 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE1(i)); dispc 571 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE2(i)); dispc 572 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DATA_CYCLE3(i)); dispc 574 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CPR)) { dispc 575 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_R(i)); dispc 576 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_G(i)); dispc 577 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CPR_COEF_B(i)); dispc 581 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); i++) { dispc 582 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA0(i)); dispc 583 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA1(i)); dispc 584 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_POSITION(i)); dispc 585 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_SIZE(i)); dispc 586 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ATTRIBUTES(i)); dispc 587 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIFO_THRESHOLD(i)); dispc 588 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ROW_INC(i)); dispc 589 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PIXEL_INC(i)); dispc 590 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_PRELOAD)) dispc 591 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PRELOAD(i)); dispc 593 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_WINDOW_SKIP(i)); dispc 594 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_TABLE_BA(i)); dispc 597 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR(i)); dispc 598 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_PICTURE_SIZE(i)); dispc 599 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU0(i)); dispc 600 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU1(i)); dispc 603 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_H(i, j)); dispc 606 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_HV(i, j)); dispc 609 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_CONV_COEF(i, j)); dispc 611 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { dispc 613 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_V(i, j)); dispc 616 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { dispc 617 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA0_UV(i)); dispc 618 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_BA1_UV(i)); dispc 619 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR2(i)); dispc 620 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU2_0(i)); dispc 621 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ACCU2_1(i)); dispc 624 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_H2(i, j)); dispc 627 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_HV2(i, j)); dispc 630 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_FIR_COEF_V2(i, j)); dispc 632 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ATTR2)) dispc 633 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, OVL_ATTRIBUTES2(i)); dispc 636 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) dispc 637 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, DIVISOR); dispc 640 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL); dispc 641 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 642 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL2); dispc 643 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) dispc 644 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, CONTROL3); dispc 646 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); dispc 652 drivers/gpu/drm/omapdrm/dss/dispc.c RR(dispc, IRQENABLE); dispc 660 drivers/gpu/drm/omapdrm/dss/dispc.c int dispc_runtime_get(struct dispc_device *dispc) dispc 666 drivers/gpu/drm/omapdrm/dss/dispc.c r = pm_runtime_get_sync(&dispc->pdev->dev); dispc 671 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_runtime_put(struct dispc_device *dispc) dispc 677 drivers/gpu/drm/omapdrm/dss/dispc.c r = pm_runtime_put_sync(&dispc->pdev->dev); dispc 681 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, dispc 687 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, dispc 690 drivers/gpu/drm/omapdrm/dss/dispc.c if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) dispc 696 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, dispc 702 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) dispc 707 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable(struct dispc_device *dispc, dispc 710 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); dispc 712 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); dispc 715 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_mgr_is_enabled(struct dispc_device *dispc, dispc 718 drivers/gpu/drm/omapdrm/dss/dispc.c return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); dispc 721 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_mgr_go_busy(struct dispc_device *dispc, dispc 724 drivers/gpu/drm/omapdrm/dss/dispc.c return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; dispc 727 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) dispc 729 drivers/gpu/drm/omapdrm/dss/dispc.c WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); dispc 730 drivers/gpu/drm/omapdrm/dss/dispc.c WARN_ON(dispc_mgr_go_busy(dispc, channel)); dispc 734 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); dispc 737 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_wb_go_busy(struct dispc_device *dispc) dispc 739 drivers/gpu/drm/omapdrm/dss/dispc.c return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; dispc 742 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_wb_go(struct dispc_device *dispc) dispc 747 drivers/gpu/drm/omapdrm/dss/dispc.c enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; dispc 752 drivers/gpu/drm/omapdrm/dss/dispc.c go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; dispc 758 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); dispc 761 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, dispc 765 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); dispc 768 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, dispc 772 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); dispc 775 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, dispc 779 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); dispc 782 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, dispc 788 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); dispc 791 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, dispc 797 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); dispc 800 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, dispc 806 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); dispc 809 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, dispc 821 drivers/gpu/drm/omapdrm/dss/dispc.c dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", dispc 839 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firh_reg(dispc, plane, i, h); dispc 840 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firhv_reg(dispc, plane, i, hv); dispc 842 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firh2_reg(dispc, plane, i, h); dispc 843 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); dispc 854 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firv_reg(dispc, plane, i, v); dispc 856 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_firv2_reg(dispc, plane, i, v); dispc 871 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, dispc 877 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); dispc 878 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); dispc 879 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); dispc 880 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); dispc 881 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); dispc 883 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); dispc 888 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc, dispc 895 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); dispc 896 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); dispc 897 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); dispc 898 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); dispc 899 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); dispc 901 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); dispc 906 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_setup_color_conv_coef(struct dispc_device *dispc) dispc 909 drivers/gpu/drm/omapdrm/dss/dispc.c int num_ovl = dispc_get_num_ovls(dispc); dispc 928 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim); dispc 930 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_writeback) dispc 931 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim); dispc 934 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_ba0(struct dispc_device *dispc, dispc 937 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); dispc 940 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_ba1(struct dispc_device *dispc, dispc 943 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); dispc 946 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, dispc 949 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); dispc 952 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, dispc 955 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); dispc 958 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_pos(struct dispc_device *dispc, dispc 969 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); dispc 972 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_input_size(struct dispc_device *dispc, dispc 979 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); dispc 981 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); dispc 984 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_output_size(struct dispc_device *dispc, dispc 995 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); dispc 997 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); dispc 1000 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_zorder(struct dispc_device *dispc, dispc 1007 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); dispc 1010 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) dispc 1014 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) dispc 1017 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); i++) dispc 1018 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); dispc 1021 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, dispc 1029 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); dispc 1032 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, dispc 1044 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); dispc 1047 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, dispc 1050 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); dispc 1053 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_row_inc(struct dispc_device *dispc, dispc 1056 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); dispc 1059 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_color_mode(struct dispc_device *dispc, dispc 1129 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); dispc 1132 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, dispc 1136 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) dispc 1140 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); dispc 1142 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); dispc 1145 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_channel_out(struct dispc_device *dispc, dispc 1167 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); dispc 1168 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { dispc 1183 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { dispc 1205 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); dispc 1208 drivers/gpu/drm/omapdrm/dss/dispc.c static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, dispc 1228 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); dispc 1233 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 1249 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_burst_size(struct dispc_device *dispc, dispc 1257 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, dispc 1261 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_configure_burst_sizes(struct dispc_device *dispc) dispc 1267 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); ++i) dispc 1268 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_burst_size(dispc, i, burst_size); dispc 1269 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_writeback) dispc 1270 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); dispc 1273 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, dispc 1277 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->feat->burst_size_unit * 8; dispc 1280 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, dispc 1286 drivers/gpu/drm/omapdrm/dss/dispc.c modes = dispc->feat->supported_color_modes[plane]; dispc 1296 drivers/gpu/drm/omapdrm/dss/dispc.c static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, dispc 1299 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->feat->supported_color_modes[plane]; dispc 1302 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable_cpr(struct dispc_device *dispc, dispc 1308 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); dispc 1311 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, dispc 1327 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); dispc 1328 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); dispc 1329 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); dispc 1332 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, dispc 1339 drivers/gpu/drm/omapdrm/dss/dispc.c val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); dispc 1341 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); dispc 1344 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_enable_replication(struct dispc_device *dispc, dispc 1356 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); dispc 1359 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_size(struct dispc_device *dispc, dispc 1364 drivers/gpu/drm/omapdrm/dss/dispc.c val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | dispc 1365 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); dispc 1367 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); dispc 1370 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_init_fifos(struct dispc_device *dispc) dispc 1378 drivers/gpu/drm/omapdrm/dss/dispc.c unit = dispc->feat->buffer_size_unit; dispc 1380 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); dispc 1382 drivers/gpu/drm/omapdrm/dss/dispc.c for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { dispc 1383 drivers/gpu/drm/omapdrm/dss/dispc.c size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), dispc 1386 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->fifo_size[fifo] = size; dispc 1392 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->fifo_assignment[fifo] = fifo; dispc 1402 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->gfx_fifo_workaround) { dispc 1405 drivers/gpu/drm/omapdrm/dss/dispc.c v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); dispc 1412 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); dispc 1414 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; dispc 1415 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; dispc 1421 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { dispc 1426 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, dispc 1429 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_fifo_threshold(dispc, i, low, high); dispc 1432 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_writeback) { dispc 1437 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, dispc 1441 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); dispc 1445 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, dispc 1451 drivers/gpu/drm/omapdrm/dss/dispc.c for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { dispc 1452 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->fifo_assignment[fifo] == plane) dispc 1453 drivers/gpu/drm/omapdrm/dss/dispc.c size += dispc->fifo_size[fifo]; dispc 1459 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, dispc 1466 drivers/gpu/drm/omapdrm/dss/dispc.c unit = dispc->feat->buffer_size_unit; dispc 1474 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, dispc 1476 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, dispc 1481 drivers/gpu/drm/omapdrm/dss/dispc.c REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), dispc 1483 drivers/gpu/drm/omapdrm/dss/dispc.c REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), dispc 1487 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), dispc 1496 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_PRELOAD) && dispc 1497 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->feat->set_max_preload && plane != OMAP_DSS_WB) dispc 1498 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), dispc 1502 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) dispc 1504 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { dispc 1510 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); dispc 1513 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, dispc 1522 drivers/gpu/drm/omapdrm/dss/dispc.c unsigned int buf_unit = dispc->feat->buffer_size_unit; dispc 1526 drivers/gpu/drm/omapdrm/dss/dispc.c burst_size = dispc_ovl_get_burst_size(dispc, plane); dispc 1527 drivers/gpu/drm/omapdrm/dss/dispc.c ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); dispc 1531 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); ++i) dispc 1532 drivers/gpu/drm/omapdrm/dss/dispc.c total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); dispc 1543 drivers/gpu/drm/omapdrm/dss/dispc.c if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { dispc 1560 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_mflag(struct dispc_device *dispc, dispc 1570 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); dispc 1573 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, dispc 1577 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), dispc 1581 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_init_mflag(struct dispc_device *dispc) dispc 1595 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, dispc 1599 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { dispc 1600 drivers/gpu/drm/omapdrm/dss/dispc.c u32 size = dispc_ovl_get_fifo_size(dispc, i); dispc 1601 drivers/gpu/drm/omapdrm/dss/dispc.c u32 unit = dispc->feat->buffer_size_unit; dispc 1604 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_mflag(dispc, i, true); dispc 1615 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_mflag_threshold(dispc, i, low, high); dispc 1618 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_writeback) { dispc 1619 drivers/gpu/drm/omapdrm/dss/dispc.c u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); dispc 1620 drivers/gpu/drm/omapdrm/dss/dispc.c u32 unit = dispc->feat->buffer_size_unit; dispc 1623 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); dispc 1634 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); dispc 1638 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_fir(struct dispc_device *dispc, dispc 1648 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, dispc 1650 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, dispc 1655 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); dispc 1658 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); dispc 1662 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, dispc 1669 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, dispc 1671 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, dispc 1677 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); dispc 1680 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, dispc 1687 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, dispc 1689 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, dispc 1695 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); dispc 1698 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, dispc 1705 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); dispc 1708 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, dispc 1715 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); dispc 1718 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_scale_param(struct dispc_device *dispc, dispc 1730 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, dispc 1732 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); dispc 1735 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, dispc 1820 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); dispc 1821 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); dispc 1824 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, dispc 1836 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, dispc 1839 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); dispc 1848 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { dispc 1855 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { dispc 1860 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); dispc 1875 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); dispc 1876 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); dispc 1879 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, dispc 1894 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) dispc 1900 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), dispc 1905 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, dispc 1948 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, dispc 1953 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), dispc 1957 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); dispc 1959 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); dispc 1962 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_scaling(struct dispc_device *dispc, dispc 1972 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, dispc 1976 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, dispc 1981 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, dispc 2038 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); dispc 2039 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) dispc 2040 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), dispc 2043 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { dispc 2050 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), dispc 2288 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, dispc 2302 drivers/gpu/drm/omapdrm/dss/dispc.c const int maxsinglelinewidth = dispc->feat->max_line_width; dispc 2309 drivers/gpu/drm/omapdrm/dss/dispc.c *core_clk = dispc->feat->calc_core_clk(pclk, in_width, dispc 2312 drivers/gpu/drm/omapdrm/dss/dispc.c *core_clk > dispc_core_clk_rate(dispc)); dispc 2337 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, dispc 2350 drivers/gpu/drm/omapdrm/dss/dispc.c const int maxsinglelinewidth = dispc->feat->max_line_width; dispc 2367 drivers/gpu/drm/omapdrm/dss/dispc.c *core_clk = dispc->feat->calc_core_clk(pclk, in_width, dispc 2381 drivers/gpu/drm/omapdrm/dss/dispc.c !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); dispc 2425 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, dispc 2439 drivers/gpu/drm/omapdrm/dss/dispc.c const int maxsinglelinewidth = dispc->feat->max_line_width; dispc 2440 drivers/gpu/drm/omapdrm/dss/dispc.c const int maxdownscale = dispc->feat->max_downscale; dispc 2445 drivers/gpu/drm/omapdrm/dss/dispc.c in_width_max = dispc_core_clk_rate(dispc) dispc 2484 drivers/gpu/drm/omapdrm/dss/dispc.c *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, dispc 2492 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_calc_scaling(struct dispc_device *dispc, dispc 2504 drivers/gpu/drm/omapdrm/dss/dispc.c int maxhdownscale = dispc->feat->max_downscale; dispc 2505 drivers/gpu/drm/omapdrm/dss/dispc.c int maxvdownscale = dispc->feat->max_downscale; dispc 2540 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_has_feature(dispc, FEAT_BURST_2D)) ? dispc 2553 drivers/gpu/drm/omapdrm/dss/dispc.c ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, dispc 2573 drivers/gpu/drm/omapdrm/dss/dispc.c core_clk, dispc_core_clk_rate(dispc)); dispc 2575 drivers/gpu/drm/omapdrm/dss/dispc.c if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { dispc 2579 drivers/gpu/drm/omapdrm/dss/dispc.c core_clk, dispc_core_clk_rate(dispc)); dispc 2588 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_setup_common(struct dispc_device *dispc, dispc 2613 drivers/gpu/drm/omapdrm/dss/dispc.c unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); dispc 2614 drivers/gpu/drm/omapdrm/dss/dispc.c unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); dispc 2649 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) dispc 2652 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, dispc 2714 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_color_mode(dispc, plane, fourcc); dispc 2716 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_configure_burst_type(dispc, plane, rotation_type); dispc 2718 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->reverse_ilace_field_order) dispc 2721 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_ba0(dispc, plane, paddr + offset0); dispc 2722 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_ba1(dispc, plane, paddr + offset1); dispc 2725 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); dispc 2726 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); dispc 2729 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->last_pixel_inc_missing) dispc 2732 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_row_inc(dispc, plane, row_inc); dispc 2733 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_pix_inc(dispc, plane, pix_inc); dispc 2738 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); dispc 2740 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_input_size(dispc, plane, in_width, in_height); dispc 2743 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_scaling(dispc, plane, in_width, in_height, dispc 2746 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_output_size(dispc, plane, out_width, out_height); dispc 2747 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_vid_color_conv(dispc, plane, cconv); dispc 2750 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, dispc 2753 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_zorder(dispc, plane, caps, zorder); dispc 2754 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); dispc 2755 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); dispc 2757 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_enable_replication(dispc, plane, caps, replication); dispc 2762 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_setup(struct dispc_device *dispc, dispc 2769 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; dispc 2778 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_set_channel_out(dispc, plane, channel); dispc 2780 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, dispc 2789 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_wb_setup(struct dispc_device *dispc, dispc 2813 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, dispc 2838 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); dispc 2846 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); dispc 2850 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); dispc 2866 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); dispc 2872 drivers/gpu/drm/omapdrm/dss/dispc.c static bool dispc_has_writeback(struct dispc_device *dispc) dispc 2874 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->feat->has_writeback; dispc 2877 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_ovl_enable(struct dispc_device *dispc, dispc 2882 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); dispc 2887 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, dispc 2890 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) dispc 2893 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); dispc 2896 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) dispc 2898 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) dispc 2901 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); dispc 2904 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) dispc 2906 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) dispc 2909 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); dispc 2912 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, dispc 2916 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); dispc 2920 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, dispc 2923 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); dispc 2926 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_set_loadmode(struct dispc_device *dispc, dispc 2929 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); dispc 2933 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_default_color(struct dispc_device *dispc, dispc 2936 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); dispc 2939 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_trans_key(struct dispc_device *dispc, dispc 2944 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); dispc 2946 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); dispc 2949 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, dispc 2952 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); dispc 2955 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, dispc 2959 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) dispc 2963 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); dispc 2965 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); dispc 2968 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_setup(struct dispc_device *dispc, dispc 2972 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_default_color(dispc, channel, info->default_color); dispc 2973 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, dispc 2975 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); dispc 2976 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, dispc 2978 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CPR)) { dispc 2979 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); dispc 2980 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); dispc 2984 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, dispc 3008 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); dispc 3011 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, dispc 3035 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_CONTROL); dispc 3038 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_CONTROL, l); dispc 3041 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, dispc 3044 drivers/gpu/drm/omapdrm/dss/dispc.c mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); dispc 3047 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_lcd_config(struct dispc_device *dispc, dispc 3051 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); dispc 3053 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); dispc 3054 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); dispc 3056 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); dispc 3058 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); dispc 3060 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); dispc 3062 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_lcd_type_tft(dispc, channel); dispc 3065 drivers/gpu/drm/omapdrm/dss/dispc.c static bool _dispc_mgr_size_ok(struct dispc_device *dispc, dispc 3068 drivers/gpu/drm/omapdrm/dss/dispc.c return width <= dispc->feat->mgr_width_max && dispc 3069 drivers/gpu/drm/omapdrm/dss/dispc.c height <= dispc->feat->mgr_height_max; dispc 3072 drivers/gpu/drm/omapdrm/dss/dispc.c static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, dispc 3076 drivers/gpu/drm/omapdrm/dss/dispc.c if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || dispc 3077 drivers/gpu/drm/omapdrm/dss/dispc.c hfp < 1 || hfp > dispc->feat->hp_max || dispc 3078 drivers/gpu/drm/omapdrm/dss/dispc.c hbp < 1 || hbp > dispc->feat->hp_max || dispc 3079 drivers/gpu/drm/omapdrm/dss/dispc.c vsw < 1 || vsw > dispc->feat->sw_max || dispc 3080 drivers/gpu/drm/omapdrm/dss/dispc.c vfp < 0 || vfp > dispc->feat->vp_max || dispc 3081 drivers/gpu/drm/omapdrm/dss/dispc.c vbp < 0 || vbp > dispc->feat->vp_max) dispc 3086 drivers/gpu/drm/omapdrm/dss/dispc.c static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, dispc 3091 drivers/gpu/drm/omapdrm/dss/dispc.c return pclk <= dispc->feat->max_lcd_pclk; dispc 3093 drivers/gpu/drm/omapdrm/dss/dispc.c return pclk <= dispc->feat->max_tv_pclk; dispc 3096 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_mgr_check_timings(struct dispc_device *dispc, dispc 3100 drivers/gpu/drm/omapdrm/dss/dispc.c if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) dispc 3103 drivers/gpu/drm/omapdrm/dss/dispc.c if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) dispc 3111 drivers/gpu/drm/omapdrm/dss/dispc.c if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, dispc 3121 drivers/gpu/drm/omapdrm/dss/dispc.c static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, dispc 3128 drivers/gpu/drm/omapdrm/dss/dispc.c timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | dispc 3129 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | dispc 3130 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); dispc 3131 drivers/gpu/drm/omapdrm/dss/dispc.c timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | dispc 3132 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | dispc 3133 drivers/gpu/drm/omapdrm/dss/dispc.c FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); dispc 3135 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); dispc 3136 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); dispc 3174 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->supports_sync_align) dispc 3177 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); dispc 3179 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->syscon_pol) { dispc 3194 drivers/gpu/drm/omapdrm/dss/dispc.c regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, dispc 3210 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_timings(struct dispc_device *dispc, dispc 3220 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_mgr_check_timings(dispc, channel, &t)) { dispc 3226 drivers/gpu/drm/omapdrm/dss/dispc.c _dispc_mgr_set_lcd_timings(dispc, channel, &t); dispc 3250 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->supports_double_pixel) dispc 3251 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, dispc 3256 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); dispc 3259 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, dispc 3266 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_DIVISORo(channel), dispc 3269 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && dispc 3271 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; dispc 3274 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, dispc 3279 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); dispc 3284 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_fclk_rate(struct dispc_device *dispc) dispc 3289 drivers/gpu/drm/omapdrm/dss/dispc.c src = dss_get_dispc_clk_source(dispc->dss); dispc 3292 drivers/gpu/drm/omapdrm/dss/dispc.c r = dss_get_dispc_clk_rate(dispc->dss); dispc 3297 drivers/gpu/drm/omapdrm/dss/dispc.c pll = dss_pll_find_by_src(dispc->dss, src); dispc 3306 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, dispc 3315 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc_fclk_rate(dispc); dispc 3317 drivers/gpu/drm/omapdrm/dss/dispc.c src = dss_get_lcd_clk_source(dispc->dss, channel); dispc 3320 drivers/gpu/drm/omapdrm/dss/dispc.c r = dss_get_dispc_clk_rate(dispc->dss); dispc 3325 drivers/gpu/drm/omapdrm/dss/dispc.c pll = dss_pll_find_by_src(dispc->dss, src); dispc 3331 drivers/gpu/drm/omapdrm/dss/dispc.c lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); dispc 3336 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, dispc 3345 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); dispc 3349 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_mgr_lclk_rate(dispc, channel); dispc 3353 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->tv_pclk_rate; dispc 3357 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) dispc 3359 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->tv_pclk_rate = pclk; dispc 3362 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) dispc 3364 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->core_clk_rate; dispc 3367 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, dispc 3375 drivers/gpu/drm/omapdrm/dss/dispc.c channel = dispc_ovl_get_channel_out(dispc, plane); dispc 3377 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc_mgr_pclk_rate(dispc, channel); dispc 3380 drivers/gpu/drm/omapdrm/dss/dispc.c static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, dispc 3388 drivers/gpu/drm/omapdrm/dss/dispc.c channel = dispc_ovl_get_channel_out(dispc, plane); dispc 3390 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc_mgr_lclk_rate(dispc, channel); dispc 3393 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_dump_clocks_channel(struct dispc_device *dispc, dispc 3402 drivers/gpu/drm/omapdrm/dss/dispc.c lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); dispc 3407 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); dispc 3410 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_lclk_rate(dispc, channel), lcd); dispc 3412 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_pclk_rate(dispc, channel), pcd); dispc 3415 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) dispc 3421 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_runtime_get(dispc)) dispc 3426 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); dispc 3430 drivers/gpu/drm/omapdrm/dss/dispc.c seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); dispc 3432 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { dispc 3434 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_DIVISOR); dispc 3438 drivers/gpu/drm/omapdrm/dss/dispc.c (dispc_fclk_rate(dispc)/lcd), lcd); dispc 3441 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); dispc 3443 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 3444 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); dispc 3445 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) dispc 3446 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); dispc 3448 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_runtime_put(dispc); dispc 3453 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc = s->private; dispc 3470 drivers/gpu/drm/omapdrm/dss/dispc.c #define DUMPREG(dispc, r) \ dispc 3471 drivers/gpu/drm/omapdrm/dss/dispc.c seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) dispc 3473 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_runtime_get(dispc)) dispc 3477 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_REVISION); dispc 3478 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_SYSCONFIG); dispc 3479 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_SYSSTATUS); dispc 3480 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_IRQSTATUS); dispc 3481 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_IRQENABLE); dispc 3482 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONTROL); dispc 3483 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONFIG); dispc 3484 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CAPABLE); dispc 3485 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_LINE_STATUS); dispc 3486 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_LINE_NUMBER); dispc 3487 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || dispc 3488 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) dispc 3489 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_GLOBAL_ALPHA); dispc 3490 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { dispc 3491 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONTROL2); dispc 3492 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONFIG2); dispc 3494 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { dispc 3495 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONTROL3); dispc 3496 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_CONFIG3); dispc 3498 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MFLAG)) dispc 3499 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); dispc 3504 drivers/gpu/drm/omapdrm/dss/dispc.c #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ dispc 3506 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_read_reg(dispc, DISPC_REG(i, r))) dispc 3511 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { dispc 3512 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); dispc 3513 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_TRANS_COLOR); dispc 3514 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_SIZE_MGR); dispc 3519 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_TIMING_H); dispc 3520 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_TIMING_V); dispc 3521 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_POL_FREQ); dispc 3522 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_DIVISORo); dispc 3524 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_DATA_CYCLE1); dispc 3525 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_DATA_CYCLE2); dispc 3526 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_DATA_CYCLE3); dispc 3528 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CPR)) { dispc 3529 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_CPR_COEF_R); dispc 3530 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_CPR_COEF_G); dispc 3531 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_CPR_COEF_B); dispc 3537 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 0; i < dispc_get_num_ovls(dispc); i++) { dispc 3538 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA0); dispc 3539 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA1); dispc 3540 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_POSITION); dispc 3541 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_SIZE); dispc 3542 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); dispc 3543 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); dispc 3544 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); dispc 3545 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ROW_INC); dispc 3546 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); dispc 3548 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_PRELOAD)) dispc 3549 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_PRELOAD); dispc 3550 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MFLAG)) dispc 3551 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); dispc 3554 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); dispc 3555 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); dispc 3559 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR); dispc 3560 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); dispc 3561 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU0); dispc 3562 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU1); dispc 3563 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { dispc 3564 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA0_UV); dispc 3565 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA1_UV); dispc 3566 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR2); dispc 3567 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); dispc 3568 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); dispc 3570 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ATTR2)) dispc 3571 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); dispc 3574 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_writeback) { dispc 3576 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA0); dispc 3577 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA1); dispc 3578 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_SIZE); dispc 3579 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); dispc 3580 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); dispc 3581 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); dispc 3582 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ROW_INC); dispc 3583 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); dispc 3585 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MFLAG)) dispc 3586 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); dispc 3588 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR); dispc 3589 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); dispc 3590 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU0); dispc 3591 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU1); dispc 3592 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { dispc 3593 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA0_UV); dispc 3594 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_BA1_UV); dispc 3595 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR2); dispc 3596 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); dispc 3597 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); dispc 3599 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_ATTR2)) dispc 3600 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); dispc 3607 drivers/gpu/drm/omapdrm/dss/dispc.c #define DUMPREG(dispc, plane, name, i) \ dispc 3610 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_read_reg(dispc, DISPC_REG(plane, name, i))) dispc 3615 drivers/gpu/drm/omapdrm/dss/dispc.c for (i = 1; i < dispc_get_num_ovls(dispc); i++) { dispc 3617 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); dispc 3620 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); dispc 3623 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); dispc 3625 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { dispc 3627 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); dispc 3630 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { dispc 3632 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); dispc 3635 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); dispc 3638 drivers/gpu/drm/omapdrm/dss/dispc.c DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); dispc 3642 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_runtime_put(dispc); dispc 3651 drivers/gpu/drm/omapdrm/dss/dispc.c int dispc_calc_clock_rates(struct dispc_device *dispc, dispc 3666 drivers/gpu/drm/omapdrm/dss/dispc.c bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, dispc 3684 drivers/gpu/drm/omapdrm/dss/dispc.c pckd_hw_min = dispc->feat->min_pcd; dispc 3687 drivers/gpu/drm/omapdrm/dss/dispc.c lck_max = dss_get_max_fck_rate(dispc->dss); dispc 3710 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) dispc 3711 drivers/gpu/drm/omapdrm/dss/dispc.c fck = dispc_core_clk_rate(dispc); dispc 3726 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_mgr_set_clock_div(struct dispc_device *dispc, dispc 3733 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, dispc 3737 drivers/gpu/drm/omapdrm/dss/dispc.c int dispc_mgr_get_clock_div(struct dispc_device *dispc, dispc 3743 drivers/gpu/drm/omapdrm/dss/dispc.c fck = dispc_fclk_rate(dispc); dispc 3745 drivers/gpu/drm/omapdrm/dss/dispc.c cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); dispc 3746 drivers/gpu/drm/omapdrm/dss/dispc.c cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); dispc 3754 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_read_irqstatus(struct dispc_device *dispc) dispc 3756 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc_read_reg(dispc, DISPC_IRQSTATUS); dispc 3759 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) dispc 3761 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); dispc 3764 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) dispc 3766 drivers/gpu/drm/omapdrm/dss/dispc.c u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); dispc 3769 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); dispc 3771 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_IRQENABLE, mask); dispc 3774 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_read_reg(dispc, DISPC_IRQENABLE); dispc 3777 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_enable_sidle(struct dispc_device *dispc) dispc 3780 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); dispc 3783 drivers/gpu/drm/omapdrm/dss/dispc.c void dispc_disable_sidle(struct dispc_device *dispc) dispc 3785 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ dispc 3788 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_mgr_gamma_size(struct dispc_device *dispc, dispc 3793 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_table) dispc 3799 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, dispc 3803 drivers/gpu/drm/omapdrm/dss/dispc.c u32 *table = dispc->gamma_table[channel]; dispc 3816 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, gdesc->reg, v); dispc 3820 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_restore_gamma_tables(struct dispc_device *dispc) dispc 3824 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_table) dispc 3827 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); dispc 3829 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); dispc 3831 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 3832 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); dispc 3834 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) dispc 3835 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); dispc 3843 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_mgr_set_gamma(struct dispc_device *dispc, dispc 3849 drivers/gpu/drm/omapdrm/dss/dispc.c u32 *table = dispc->gamma_table[channel]; dispc 3855 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_table) dispc 3887 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->is_enabled) dispc 3888 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_write_gamma_table(dispc, channel); dispc 3891 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_init_gamma_tables(struct dispc_device *dispc) dispc 3895 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_table) dispc 3898 drivers/gpu/drm/omapdrm/dss/dispc.c for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { dispc 3903 drivers/gpu/drm/omapdrm/dss/dispc.c !dispc_has_feature(dispc, FEAT_MGR_LCD2)) dispc 3907 drivers/gpu/drm/omapdrm/dss/dispc.c !dispc_has_feature(dispc, FEAT_MGR_LCD3)) dispc 3910 drivers/gpu/drm/omapdrm/dss/dispc.c gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, dispc 3915 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->gamma_table[channel] = gt; dispc 3917 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_gamma(dispc, channel, NULL, 0); dispc 3922 drivers/gpu/drm/omapdrm/dss/dispc.c static void _omap_dispc_initial_config(struct dispc_device *dispc) dispc 3927 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { dispc 3928 drivers/gpu/drm/omapdrm/dss/dispc.c l = dispc_read_reg(dispc, DISPC_DIVISOR); dispc 3932 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_DIVISOR, l); dispc 3934 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->core_clk_rate = dispc_fclk_rate(dispc); dispc 3938 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->has_gamma_table) dispc 3939 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); dispc 3945 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_FUNCGATED) || dispc 3946 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->feat->has_gamma_table) dispc 3947 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); dispc 3949 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_setup_color_conv_coef(dispc); dispc 3951 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); dispc 3953 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_init_fifos(dispc); dispc 3955 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_configure_burst_sizes(dispc); dispc 3957 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_enable_zorder_planes(dispc); dispc 3959 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->feat->mstandby_workaround) dispc 3960 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); dispc 3962 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc_has_feature(dispc, FEAT_MFLAG)) dispc 3963 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_init_mflag(dispc); dispc 4482 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc = arg; dispc 4484 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->is_enabled) dispc 4487 drivers/gpu/drm/omapdrm/dss/dispc.c return dispc->user_handler(irq, dispc->user_data); dispc 4490 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, dispc 4495 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->user_handler != NULL) dispc 4498 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_handler = handler; dispc 4499 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_data = dev_id; dispc 4504 drivers/gpu/drm/omapdrm/dss/dispc.c r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, dispc 4505 drivers/gpu/drm/omapdrm/dss/dispc.c IRQF_SHARED, "OMAP DISPC", dispc); dispc 4507 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_handler = NULL; dispc 4508 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_data = NULL; dispc 4514 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) dispc 4516 drivers/gpu/drm/omapdrm/dss/dispc.c devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); dispc 4518 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_handler = NULL; dispc 4519 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->user_data = NULL; dispc 4522 drivers/gpu/drm/omapdrm/dss/dispc.c static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) dispc 4527 drivers/gpu/drm/omapdrm/dss/dispc.c of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", dispc 4604 drivers/gpu/drm/omapdrm/dss/dispc.c static int dispc_errata_i734_wa_init(struct dispc_device *dispc) dispc 4606 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_i734_bug) dispc 4612 drivers/gpu/drm/omapdrm/dss/dispc.c i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, dispc 4615 drivers/gpu/drm/omapdrm/dss/dispc.c dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", dispc 4623 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) dispc 4625 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_i734_bug) dispc 4628 drivers/gpu/drm/omapdrm/dss/dispc.c dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, dispc 4632 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_errata_i734_wa(struct dispc_device *dispc) dispc 4634 drivers/gpu/drm/omapdrm/dss/dispc.c u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, dispc 4641 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc->feat->has_gamma_i734_bug) dispc 4644 drivers/gpu/drm/omapdrm/dss/dispc.c gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); dispc 4651 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); dispc 4654 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, dispc 4656 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); dispc 4659 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); dispc 4660 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), dispc 4662 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); dispc 4663 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); dispc 4665 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clear_irqstatus(dispc, framedone_irq); dispc 4668 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); dispc 4669 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); dispc 4676 drivers/gpu/drm/omapdrm/dss/dispc.c while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { dispc 4678 drivers/gpu/drm/omapdrm/dss/dispc.c dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", dispc 4683 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); dispc 4686 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clear_irqstatus(dispc, 0xffffffff); dispc 4689 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); dispc 4757 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc; dispc 4763 drivers/gpu/drm/omapdrm/dss/dispc.c dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); dispc 4764 drivers/gpu/drm/omapdrm/dss/dispc.c if (!dispc) dispc 4767 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->pdev = pdev; dispc 4768 drivers/gpu/drm/omapdrm/dss/dispc.c platform_set_drvdata(pdev, dispc); dispc 4769 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->dss = dss; dispc 4771 drivers/gpu/drm/omapdrm/dss/dispc.c spin_lock_init(&dispc->control_lock); dispc 4779 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->feat = soc->data; dispc 4781 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; dispc 4783 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_errata_i734_wa_init(dispc); dispc 4787 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); dispc 4788 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); dispc 4789 drivers/gpu/drm/omapdrm/dss/dispc.c if (IS_ERR(dispc->base)) { dispc 4790 drivers/gpu/drm/omapdrm/dss/dispc.c r = PTR_ERR(dispc->base); dispc 4794 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->irq = platform_get_irq(dispc->pdev, 0); dispc 4795 drivers/gpu/drm/omapdrm/dss/dispc.c if (dispc->irq < 0) { dispc 4802 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); dispc 4803 drivers/gpu/drm/omapdrm/dss/dispc.c if (IS_ERR(dispc->syscon_pol)) { dispc 4805 drivers/gpu/drm/omapdrm/dss/dispc.c r = PTR_ERR(dispc->syscon_pol); dispc 4810 drivers/gpu/drm/omapdrm/dss/dispc.c &dispc->syscon_pol_offset)) { dispc 4817 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_init_gamma_tables(dispc); dispc 4823 drivers/gpu/drm/omapdrm/dss/dispc.c r = dispc_runtime_get(dispc); dispc 4827 drivers/gpu/drm/omapdrm/dss/dispc.c _omap_dispc_initial_config(dispc); dispc 4829 drivers/gpu/drm/omapdrm/dss/dispc.c rev = dispc_read_reg(dispc, DISPC_REVISION); dispc 4833 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_runtime_put(dispc); dispc 4835 drivers/gpu/drm/omapdrm/dss/dispc.c dss->dispc = dispc; dispc 4838 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, dispc 4839 drivers/gpu/drm/omapdrm/dss/dispc.c dispc); dispc 4846 drivers/gpu/drm/omapdrm/dss/dispc.c kfree(dispc); dispc 4852 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc = dev_get_drvdata(dev); dispc 4853 drivers/gpu/drm/omapdrm/dss/dispc.c struct dss_device *dss = dispc->dss; dispc 4855 drivers/gpu/drm/omapdrm/dss/dispc.c dss_debugfs_remove_file(dispc->debugfs); dispc 4857 drivers/gpu/drm/omapdrm/dss/dispc.c dss->dispc = NULL; dispc 4862 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_errata_i734_wa_fini(dispc); dispc 4864 drivers/gpu/drm/omapdrm/dss/dispc.c kfree(dispc); dispc 4885 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc = dev_get_drvdata(dev); dispc 4887 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->is_enabled = false; dispc 4891 drivers/gpu/drm/omapdrm/dss/dispc.c synchronize_irq(dispc->irq); dispc 4893 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_save_context(dispc); dispc 4900 drivers/gpu/drm/omapdrm/dss/dispc.c struct dispc_device *dispc = dev_get_drvdata(dev); dispc 4908 drivers/gpu/drm/omapdrm/dss/dispc.c if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { dispc 4909 drivers/gpu/drm/omapdrm/dss/dispc.c _omap_dispc_initial_config(dispc); dispc 4911 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_errata_i734_wa(dispc); dispc 4913 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_restore_context(dispc); dispc 4915 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_restore_gamma_tables(dispc); dispc 4918 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->is_enabled = true; dispc 176 drivers/gpu/drm/omapdrm/dss/dpi.c static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 182 drivers/gpu/drm/omapdrm/dss/dpi.c ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; dispc 184 drivers/gpu/drm/omapdrm/dss/dpi.c return dispc_div_calc(ctx->dpi->dss->dispc, dispc, dispc 212 drivers/gpu/drm/omapdrm/dss/dpi.c return dispc_div_calc(ctx->dpi->dss->dispc, fck, dispc 383 drivers/gpu/drm/omapdrm/dss/dpi.c r = dispc_runtime_get(dpi->dss->dispc); dispc 419 drivers/gpu/drm/omapdrm/dss/dpi.c dispc_runtime_put(dpi->dss->dispc); dispc 441 drivers/gpu/drm/omapdrm/dss/dpi.c dispc_runtime_put(dpi->dss->dispc); dispc 1339 drivers/gpu/drm/omapdrm/dss/dsi.c dispc_pck_free_enable(dsi->dss->dispc, 1); dispc 1344 drivers/gpu/drm/omapdrm/dss/dsi.c dispc_pck_free_enable(dsi->dss->dispc, 0); dispc 1350 drivers/gpu/drm/omapdrm/dss/dsi.c dispc_pck_free_enable(dsi->dss->dispc, 0); dispc 3864 drivers/gpu/drm/omapdrm/dss/dsi.c dispc_disable_sidle(dsi->dss->dispc); dispc 3897 drivers/gpu/drm/omapdrm/dss/dsi.c dispc_enable_sidle(dsi->dss->dispc); dispc 3978 drivers/gpu/drm/omapdrm/dss/dsi.c r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); dispc 4318 drivers/gpu/drm/omapdrm/dss/dsi.c static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 4324 drivers/gpu/drm/omapdrm/dss/dsi.c ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; dispc 4326 drivers/gpu/drm/omapdrm/dss/dsi.c return dispc_div_calc(ctx->dsi->dss->dispc, dispc, dispc 4608 drivers/gpu/drm/omapdrm/dss/dsi.c static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 4615 drivers/gpu/drm/omapdrm/dss/dsi.c ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; dispc 4627 drivers/gpu/drm/omapdrm/dss/dsi.c return dispc_div_calc(ctx->dsi->dss->dispc, dispc, dispc 266 drivers/gpu/drm/omapdrm/dss/dss.c dispc_pck_free_enable(dss->dispc, 1); dispc 296 drivers/gpu/drm/omapdrm/dss/dss.c dispc_lcd_enable_signal(dss->dispc, 1); dispc 310 drivers/gpu/drm/omapdrm/dss/dss.c dispc_lcd_enable_signal(dss->dispc, 0); dispc 315 drivers/gpu/drm/omapdrm/dss/dss.c dispc_pck_free_enable(dss->dispc, 0); dispc 322 drivers/gpu/drm/omapdrm/dss/dss.c dispc_lcd_enable_signal(dss->dispc, 0); dispc 324 drivers/gpu/drm/omapdrm/dss/dss.c dispc_pck_free_enable(dss->dispc, 0); dispc 385 drivers/gpu/drm/omapdrm/dss/dss.c dispc_dump_clocks(dss->dispc, s); dispc 259 drivers/gpu/drm/omapdrm/dss/dss.h struct dispc_device *dispc; dispc 391 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s); dispc 393 drivers/gpu/drm/omapdrm/dss/dss.h int dispc_runtime_get(struct dispc_device *dispc); dispc 394 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_runtime_put(struct dispc_device *dispc); dispc 396 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_enable_sidle(struct dispc_device *dispc); dispc 397 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_disable_sidle(struct dispc_device *dispc); dispc 399 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable); dispc 400 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_pck_free_enable(struct dispc_device *dispc, bool enable); dispc 401 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable); dispc 405 drivers/gpu/drm/omapdrm/dss/dss.h bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, dispc 409 drivers/gpu/drm/omapdrm/dss/dss.h int dispc_calc_clock_rates(struct dispc_device *dispc, dispc 414 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, dispc 416 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, dispc 421 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_mgr_set_clock_div(struct dispc_device *dispc, dispc 424 drivers/gpu/drm/omapdrm/dss/dss.h int dispc_mgr_get_clock_div(struct dispc_device *dispc, dispc 427 drivers/gpu/drm/omapdrm/dss/dss.h void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk); dispc 443 drivers/gpu/drm/omapdrm/dss/dss.h typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, dispc 249 drivers/gpu/drm/omapdrm/dss/hdmi4.c dispc_set_tv_pclk(hdmi->dss->dispc, mode->clock * 1000); dispc 248 drivers/gpu/drm/omapdrm/dss/hdmi5.c dispc_set_tv_pclk(hdmi->dss->dispc, mode->clock * 1000); dispc 560 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*read_irqstatus)(struct dispc_device *dispc); dispc 561 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask); dispc 562 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*write_irqenable)(struct dispc_device *dispc, u32 mask); dispc 564 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler, dispc 566 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*free_irq)(struct dispc_device *dispc, void *dev_id); dispc 568 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*runtime_get)(struct dispc_device *dispc); dispc 569 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*runtime_put)(struct dispc_device *dispc); dispc 571 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*get_num_ovls)(struct dispc_device *dispc); dispc 572 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*get_num_mgrs)(struct dispc_device *dispc); dispc 574 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc); dispc 576 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_enable)(struct dispc_device *dispc, dispc 578 drivers/gpu/drm/omapdrm/dss/omapdss.h bool (*mgr_is_enabled)(struct dispc_device *dispc, dispc 580 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc, dispc 582 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc, dispc 584 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc, dispc 586 drivers/gpu/drm/omapdrm/dss/omapdss.h bool (*mgr_go_busy)(struct dispc_device *dispc, dispc 588 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel); dispc 589 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_set_lcd_config)(struct dispc_device *dispc, dispc 592 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*mgr_check_timings)(struct dispc_device *dispc, dispc 595 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_set_timings)(struct dispc_device *dispc, dispc 598 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel, dispc 600 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*mgr_gamma_size)(struct dispc_device *dispc, dispc 602 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*mgr_set_gamma)(struct dispc_device *dispc, dispc 607 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane, dispc 609 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane, dispc 614 drivers/gpu/drm/omapdrm/dss/omapdss.h const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc, dispc 617 drivers/gpu/drm/omapdrm/dss/omapdss.h u32 (*wb_get_framedone_irq)(struct dispc_device *dispc); dispc 618 drivers/gpu/drm/omapdrm/dss/omapdss.h int (*wb_setup)(struct dispc_device *dispc, dispc 622 drivers/gpu/drm/omapdrm/dss/omapdss.h bool (*has_writeback)(struct dispc_device *dispc); dispc 623 drivers/gpu/drm/omapdrm/dss/omapdss.h bool (*wb_go_busy)(struct dispc_device *dispc); dispc 624 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*wb_go)(struct dispc_device *dispc); dispc 64 drivers/gpu/drm/omapdrm/dss/sdi.c return dispc_div_calc(ctx->sdi->dss->dispc, fck, dispc 132 drivers/gpu/drm/omapdrm/dss/sdi.c r = dispc_runtime_get(sdi->dss->dispc); dispc 159 drivers/gpu/drm/omapdrm/dss/sdi.c dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, dispc 179 drivers/gpu/drm/omapdrm/dss/sdi.c dispc_runtime_put(sdi->dss->dispc); dispc 192 drivers/gpu/drm/omapdrm/dss/sdi.c dispc_runtime_put(sdi->dss->dispc); dispc 571 drivers/gpu/drm/omapdrm/dss/venc.c dispc_set_tv_pclk(venc->dss->dispc, 13500000); dispc 106 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, true); dispc 131 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); dispc 144 drivers/gpu/drm/omapdrm/omap_crtc.c framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, dispc 146 drivers/gpu/drm/omapdrm/omap_crtc.c vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); dispc 166 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); dispc 189 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, dispc 224 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, dispc 303 drivers/gpu/drm/omapdrm/omap_crtc.c if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) { dispc 407 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info); dispc 448 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->runtime_get(priv->dispc); dispc 486 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->runtime_put(priv->dispc); dispc 506 drivers/gpu/drm/omapdrm/omap_crtc.c r = priv->dispc_ops->mgr_check_timings(priv->dispc, dispc 622 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel, dispc 647 drivers/gpu/drm/omapdrm/omap_crtc.c priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel); dispc 836 drivers/gpu/drm/omapdrm/omap_crtc.c if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) { dispc 70 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->runtime_get(priv->dispc); dispc 114 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->runtime_put(priv->dispc); dispc 196 drivers/gpu/drm/omapdrm/omap_drv.c unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); dispc 233 drivers/gpu/drm/omapdrm/omap_drv.c int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc); dispc 234 drivers/gpu/drm/omapdrm/omap_drv.c int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); dispc 575 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc = dispc_get_dispc(priv->dss); dispc 590 drivers/gpu/drm/omapdrm/omap_drv.c priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc); dispc 49 drivers/gpu/drm/omapdrm/omap_drv.h struct dispc_device *dispc; dispc 32 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->write_irqenable(priv->dispc, irqmask); dispc 86 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel); dispc 124 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, dispc 151 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, dispc 216 drivers/gpu/drm/omapdrm/omap_irq.c irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); dispc 217 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); dispc 218 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ dispc 226 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { dispc 231 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) dispc 234 drivers/gpu/drm/omapdrm/omap_irq.c if (irqstatus & priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel)) dispc 268 drivers/gpu/drm/omapdrm/omap_irq.c unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); dispc 286 drivers/gpu/drm/omapdrm/omap_irq.c priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i); dispc 288 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->runtime_get(priv->dispc); dispc 289 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff); dispc 290 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->runtime_put(priv->dispc); dispc 292 drivers/gpu/drm/omapdrm/omap_irq.c ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev); dispc 310 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->free_irq(priv->dispc, dev); dispc 73 drivers/gpu/drm/omapdrm/omap_plane.c ret = priv->dispc_ops->ovl_setup(priv->dispc, omap_plane->id, &info, dispc 79 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); dispc 83 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, true); dispc 96 drivers/gpu/drm/omapdrm/omap_plane.c priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); dispc 255 drivers/gpu/drm/omapdrm/omap_plane.c unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); dispc 274 drivers/gpu/drm/omapdrm/omap_plane.c formats = priv->dispc_ops->ovl_get_color_modes(priv->dispc, id); dispc 127 drivers/video/fbdev/omap2/omapfb/dss/dispc.c } dispc; dispc 253 drivers/video/fbdev/omap2/omapfb/dss/dispc.c __raw_writel(val, dispc.base + idx); dispc 258 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return __raw_readl(dispc.base + idx); dispc 274 drivers/video/fbdev/omap2/omapfb/dss/dispc.c spin_lock_irqsave(&dispc.control_lock, flags); dispc 279 drivers/video/fbdev/omap2/omapfb/dss/dispc.c spin_unlock_irqrestore(&dispc.control_lock, flags); dispc 283 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) dispc 285 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) dispc 389 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.ctx_valid = true; dispc 400 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!dispc.ctx_valid) dispc 522 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pm_runtime_get_sync(&dispc.pdev->dev); dispc 534 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pm_runtime_put_sync(&dispc.pdev->dev); dispc 547 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) dispc 721 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->has_writeback) dispc 1056 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->has_writeback) dispc 1138 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | dispc 1139 drivers/video/fbdev/omap2/omapfb/dss/dispc.c FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); dispc 1156 drivers/video/fbdev/omap2/omapfb/dss/dispc.c for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { dispc 1159 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.fifo_size[fifo] = size; dispc 1165 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.fifo_assignment[fifo] = fifo; dispc 1175 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->gfx_fifo_workaround) { dispc 1187 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; dispc 1188 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; dispc 1205 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->has_writeback) { dispc 1222 drivers/video/fbdev/omap2/omapfb/dss/dispc.c for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { dispc 1223 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.fifo_assignment[fifo] == plane) dispc 1224 drivers/video/fbdev/omap2/omapfb/dss/dispc.c size += dispc.fifo_size[fifo]; dispc 1263 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && dispc 1382 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->has_writeback) { dispc 2302 drivers/video/fbdev/omap2/omapfb/dss/dispc.c *core_clk = dispc.feat->calc_core_clk(pclk, in_width, dispc 2357 drivers/video/fbdev/omap2/omapfb/dss/dispc.c *core_clk = dispc.feat->calc_core_clk(pclk, in_width, dispc 2452 drivers/video/fbdev/omap2/omapfb/dss/dispc.c *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, dispc 2512 drivers/video/fbdev/omap2/omapfb/dss/dispc.c ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, dispc 2749 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->last_pixel_inc_missing) dispc 3082 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return width <= dispc.feat->mgr_width_max && dispc 3083 drivers/video/fbdev/omap2/omapfb/dss/dispc.c height <= dispc.feat->mgr_height_max; dispc 3089 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (hsw < 1 || hsw > dispc.feat->sw_max || dispc 3090 drivers/video/fbdev/omap2/omapfb/dss/dispc.c hfp < 1 || hfp > dispc.feat->hp_max || dispc 3091 drivers/video/fbdev/omap2/omapfb/dss/dispc.c hbp < 1 || hbp > dispc.feat->hp_max || dispc 3092 drivers/video/fbdev/omap2/omapfb/dss/dispc.c vsw < 1 || vsw > dispc.feat->sw_max || dispc 3093 drivers/video/fbdev/omap2/omapfb/dss/dispc.c vfp < 0 || vfp > dispc.feat->vp_max || dispc 3094 drivers/video/fbdev/omap2/omapfb/dss/dispc.c vbp < 0 || vbp > dispc.feat->vp_max) dispc 3103 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return pclk <= dispc.feat->max_lcd_pclk ? true : false; dispc 3105 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return pclk <= dispc.feat->max_tv_pclk ? true : false; dispc 3143 drivers/video/fbdev/omap2/omapfb/dss/dispc.c timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | dispc 3144 drivers/video/fbdev/omap2/omapfb/dss/dispc.c FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | dispc 3145 drivers/video/fbdev/omap2/omapfb/dss/dispc.c FLD_VAL(hbp-1, dispc.feat->bp_start, 20); dispc 3146 drivers/video/fbdev/omap2/omapfb/dss/dispc.c timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | dispc 3147 drivers/video/fbdev/omap2/omapfb/dss/dispc.c FLD_VAL(vfp, dispc.feat->fp_start, 8) | dispc 3148 drivers/video/fbdev/omap2/omapfb/dss/dispc.c FLD_VAL(vbp, dispc.feat->bp_start, 20); dispc 3219 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->supports_sync_align) dispc 3224 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.syscon_pol) { dispc 3239 drivers/video/fbdev/omap2/omapfb/dss/dispc.c regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, dispc 3298 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.core_clk_rate = dispc_fclk_rate() / lck_div; dispc 3398 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return dispc.tv_pclk_rate; dispc 3404 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.tv_pclk_rate = pclk; dispc 3409 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return dispc.core_clk_rate; dispc 3614 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->has_writeback) { dispc 3703 drivers/video/fbdev/omap2/omapfb/dss/dispc.c bool dispc_div_calc(unsigned long dispc, dispc 3729 drivers/video/fbdev/omap2/omapfb/dss/dispc.c lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); dispc 3730 drivers/video/fbdev/omap2/omapfb/dss/dispc.c lckd_stop = min(dispc / pck_min, 255ul); dispc 3733 drivers/video/fbdev/omap2/omapfb/dss/dispc.c lck = dispc / lckd; dispc 3839 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.core_clk_rate = dispc_fclk_rate(); dispc 3856 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.feat->mstandby_workaround) dispc 4001 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!dispc.is_enabled) dispc 4004 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return dispc.user_handler(irq, dispc.user_data); dispc 4011 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.user_handler != NULL) dispc 4014 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_handler = handler; dispc 4015 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_data = dev_id; dispc 4020 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, dispc 4021 drivers/video/fbdev/omap2/omapfb/dss/dispc.c IRQF_SHARED, "OMAP DISPC", &dispc); dispc 4023 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_handler = NULL; dispc 4024 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_data = NULL; dispc 4033 drivers/video/fbdev/omap2/omapfb/dss/dispc.c devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); dispc 4035 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_handler = NULL; dispc 4036 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.user_data = NULL; dispc 4049 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.pdev = pdev; dispc 4051 drivers/video/fbdev/omap2/omapfb/dss/dispc.c spin_lock_init(&dispc.control_lock); dispc 4053 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.feat = dispc_get_features(); dispc 4054 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!dispc.feat) dispc 4057 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); dispc 4063 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, dispc 4065 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!dispc.base) { dispc 4070 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.irq = platform_get_irq(dispc.pdev, 0); dispc 4071 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (dispc.irq < 0) { dispc 4077 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); dispc 4078 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (IS_ERR(dispc.syscon_pol)) { dispc 4080 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return PTR_ERR(dispc.syscon_pol); dispc 4084 drivers/video/fbdev/omap2/omapfb/dss/dispc.c &dispc.syscon_pol_offset)) { dispc 4141 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.is_enabled = false; dispc 4145 drivers/video/fbdev/omap2/omapfb/dss/dispc.c synchronize_irq(dispc.irq); dispc 4166 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.is_enabled = true; dispc 172 drivers/video/fbdev/omap2/omapfb/dss/dpi.c static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 186 drivers/video/fbdev/omap2/omapfb/dss/dpi.c ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; dispc 188 drivers/video/fbdev/omap2/omapfb/dss/dpi.c return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, dispc 4422 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 4428 drivers/video/fbdev/omap2/omapfb/dss/dsi.c ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; dispc 4430 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, dispc 4709 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, dispc 4716 drivers/video/fbdev/omap2/omapfb/dss/dsi.c ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; dispc 4728 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, dispc 385 drivers/video/fbdev/omap2/omapfb/dss/dss.h bool dispc_div_calc(unsigned long dispc, dispc 479 drivers/video/fbdev/omap2/omapfb/dss/dss.h typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,