disp_ttu_regs 51 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); disp_ttu_regs 1526 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l disp_ttu_regs 1528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l disp_ttu_regs 1530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c disp_ttu_regs 1532 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c disp_ttu_regs 1534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs 1536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 disp_ttu_regs 1538 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs 1540 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 disp_ttu_regs 1542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_low_wm = 0; disp_ttu_regs 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs 1544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal disp_ttu_regs 1548 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_flip = 14; disp_ttu_regs 1549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_fixed_l = 8; disp_ttu_regs 1550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_fixed_c = 8; disp_ttu_regs 1551 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_level_fixed_cur0 = 8; disp_ttu_regs 1552 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_ramp_disable_l = 0; disp_ttu_regs 1553 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs 1554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->qos_ramp_disable_cur0 = 0; disp_ttu_regs 1556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; disp_ttu_regs 1557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); disp_ttu_regs 1559 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c print__ttu_regs_st(mode_lib, *disp_ttu_regs); disp_ttu_regs 51 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); disp_ttu_regs 1526 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l disp_ttu_regs 1528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l disp_ttu_regs 1530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c disp_ttu_regs 1532 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c disp_ttu_regs 1534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs 1536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 disp_ttu_regs 1538 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs 1540 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 disp_ttu_regs 1542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_low_wm = 0; disp_ttu_regs 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs 1544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal disp_ttu_regs 1548 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_flip = 14; disp_ttu_regs 1549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_fixed_l = 8; disp_ttu_regs 1550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_fixed_c = 8; disp_ttu_regs 1551 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_level_fixed_cur0 = 8; disp_ttu_regs 1552 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_ramp_disable_l = 0; disp_ttu_regs 1553 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs 1554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->qos_ramp_disable_cur0 = 0; disp_ttu_regs 1556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; disp_ttu_regs 1557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); disp_ttu_regs 1559 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c print__ttu_regs_st(mode_lib, *disp_ttu_regs); disp_ttu_regs 818 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 951 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); disp_ttu_regs 1626 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l disp_ttu_regs 1628 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l disp_ttu_regs 1630 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c disp_ttu_regs 1632 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c disp_ttu_regs 1634 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs 1636 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 disp_ttu_regs 1638 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs 1640 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 disp_ttu_regs 1642 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_low_wm = 0; disp_ttu_regs 1643 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs 1644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal disp_ttu_regs 1646 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); disp_ttu_regs 1648 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_flip = 14; disp_ttu_regs 1649 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_fixed_l = 8; disp_ttu_regs 1650 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_fixed_c = 8; disp_ttu_regs 1651 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_level_fixed_cur0 = 8; disp_ttu_regs 1652 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_ramp_disable_l = 0; disp_ttu_regs 1653 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs 1654 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->qos_ramp_disable_cur0 = 0; disp_ttu_regs 1656 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; disp_ttu_regs 1657 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); disp_ttu_regs 1659 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c print__ttu_regs_st(mode_lib, *disp_ttu_regs); disp_ttu_regs 982 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs, disp_ttu_regs 1117 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); disp_ttu_regs 1762 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l disp_ttu_regs 1764 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l disp_ttu_regs 1799 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_pre_c = disp_ttu_regs 1801 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c disp_ttu_regs 1851 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs 1886 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_cur0 = disp_ttu_regs 1890 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0; disp_ttu_regs 1891 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0; disp_ttu_regs 1895 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_low_wm = 0; disp_ttu_regs 1896 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); disp_ttu_regs 1897 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal disp_ttu_regs 1899 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); disp_ttu_regs 1901 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_flip = 14; disp_ttu_regs 1902 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_fixed_l = 8; disp_ttu_regs 1903 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_fixed_c = 8; disp_ttu_regs 1904 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_level_fixed_cur0 = 8; disp_ttu_regs 1905 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_ramp_disable_l = 0; disp_ttu_regs 1906 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_ramp_disable_c = 0; disp_ttu_regs 1907 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->qos_ramp_disable_cur0 = 0; disp_ttu_regs 1909 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; disp_ttu_regs 1910 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); disp_ttu_regs 1912 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c print__ttu_regs_st(mode_lib, *disp_ttu_regs);