disp_int         3214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
disp_int         3219 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
disp_int         3231 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
disp_int         3251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	uint32_t disp_int, mask;
disp_int         3260 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
disp_int         3263 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	if (disp_int & mask) {
disp_int         3340 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
disp_int         3346 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
disp_int         3358 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
disp_int         3378 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	uint32_t disp_int, mask;
disp_int         3387 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
disp_int         3390 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	if (disp_int & mask) {
disp_int         2933 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
disp_int         2939 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
disp_int         2950 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
disp_int         3045 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	uint32_t disp_int, mask, tmp;
disp_int         3054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
disp_int         3057 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	if (disp_int & mask) {
disp_int         3025 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
disp_int         3031 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
disp_int         3042 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
disp_int         3137 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	uint32_t disp_int, mask, tmp;
disp_int         3146 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
disp_int         3149 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	if (disp_int & mask) {
disp_int         7304 drivers/gpu/drm/radeon/cik.c 	rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
disp_int         7335 drivers/gpu/drm/radeon/cik.c 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
disp_int         7337 drivers/gpu/drm/radeon/cik.c 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
disp_int         7378 drivers/gpu/drm/radeon/cik.c 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
disp_int         7408 drivers/gpu/drm/radeon/cik.c 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
disp_int         7599 drivers/gpu/drm/radeon/cik.c 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
disp_int         7609 drivers/gpu/drm/radeon/cik.c 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
disp_int         7614 drivers/gpu/drm/radeon/cik.c 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
disp_int         7617 drivers/gpu/drm/radeon/cik.c 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
disp_int         7789 drivers/gpu/drm/radeon/cik.c 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
disp_int         7792 drivers/gpu/drm/radeon/cik.c 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
disp_int         7843 drivers/gpu/drm/radeon/cik.c 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
disp_int         7846 drivers/gpu/drm/radeon/cik.c 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
disp_int         4616 drivers/gpu/drm/radeon/evergreen.c 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
disp_int         4620 drivers/gpu/drm/radeon/evergreen.c 		disp_int[i] = RREG32(evergreen_disp_int_status[i]);
disp_int         4635 drivers/gpu/drm/radeon/evergreen.c 			if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
disp_int         4638 drivers/gpu/drm/radeon/evergreen.c 			if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
disp_int         4645 drivers/gpu/drm/radeon/evergreen.c 		if (disp_int[i] & DC_HPD1_INTERRUPT)
disp_int         4650 drivers/gpu/drm/radeon/evergreen.c 		if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
disp_int         4703 drivers/gpu/drm/radeon/evergreen.c 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
disp_int         4775 drivers/gpu/drm/radeon/evergreen.c 			if (!(disp_int[crtc_idx] & mask)) {
disp_int         4780 drivers/gpu/drm/radeon/evergreen.c 			disp_int[crtc_idx] &= ~mask;
disp_int         4813 drivers/gpu/drm/radeon/evergreen.c 			if (!(disp_int[hpd_idx] & mask))
disp_int         4816 drivers/gpu/drm/radeon/evergreen.c 			disp_int[hpd_idx] &= ~mask;
disp_int         3920 drivers/gpu/drm/radeon/r600.c 		rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
disp_int         3931 drivers/gpu/drm/radeon/r600.c 		rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
disp_int         3944 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
disp_int         3946 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
disp_int         3948 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
disp_int         3950 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
disp_int         3952 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
disp_int         3963 drivers/gpu/drm/radeon/r600.c 	if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
disp_int         4138 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
disp_int         4148 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
disp_int         4153 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
disp_int         4156 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
disp_int         4168 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
disp_int         4178 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
disp_int         4183 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
disp_int         4186 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
disp_int         4208 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
disp_int         4211 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
disp_int         4216 drivers/gpu/drm/radeon/r600.c 				if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
disp_int         4219 drivers/gpu/drm/radeon/r600.c 				rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
disp_int          749 drivers/gpu/drm/radeon/radeon.h 	u32 disp_int;
disp_int          754 drivers/gpu/drm/radeon/radeon.h 	u32 disp_int;
disp_int          764 drivers/gpu/drm/radeon/radeon.h 	u32 disp_int[6];
disp_int          770 drivers/gpu/drm/radeon/radeon.h 	u32 disp_int;
disp_int          720 drivers/gpu/drm/radeon/rs600.c 		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
disp_int          721 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          725 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          729 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          734 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          740 drivers/gpu/drm/radeon/rs600.c 		rdev->irq.stat_regs.r500.disp_int = 0;
disp_int          780 drivers/gpu/drm/radeon/rs600.c 	    !rdev->irq.stat_regs.r500.disp_int &&
disp_int          785 drivers/gpu/drm/radeon/rs600.c 	       rdev->irq.stat_regs.r500.disp_int ||
disp_int          792 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          801 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          810 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int          814 drivers/gpu/drm/radeon/rs600.c 		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
disp_int         6148 drivers/gpu/drm/radeon/si.c 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
disp_int         6155 drivers/gpu/drm/radeon/si.c 		disp_int[i] = RREG32(si_disp_int_status[i]);
disp_int         6169 drivers/gpu/drm/radeon/si.c 			if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
disp_int         6172 drivers/gpu/drm/radeon/si.c 			if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
disp_int         6179 drivers/gpu/drm/radeon/si.c 		if (disp_int[i] & DC_HPD1_INTERRUPT)
disp_int         6184 drivers/gpu/drm/radeon/si.c 		if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
disp_int         6247 drivers/gpu/drm/radeon/si.c 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
disp_int         6318 drivers/gpu/drm/radeon/si.c 			if (!(disp_int[crtc_idx] & mask)) {
disp_int         6323 drivers/gpu/drm/radeon/si.c 			disp_int[crtc_idx] &= ~mask;
disp_int         6356 drivers/gpu/drm/radeon/si.c 			if (!(disp_int[hpd_idx] & mask))
disp_int         6359 drivers/gpu/drm/radeon/si.c 			disp_int[hpd_idx] &= ~mask;