disp_info         197 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct msm_display_info disp_info;
disp_info         465 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct msm_display_info *disp_info;
disp_info         474 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	disp_info = &dpu_enc->disp_info;
disp_info         476 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
disp_info         623 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			struct msm_display_info *disp_info)
disp_info         632 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (!dpu_enc || !disp_info) {
disp_info         634 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 					dpu_enc != NULL, disp_info != NULL);
disp_info         660 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
disp_info         665 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		if (disp_info->is_te_using_watchdog_timer)
disp_info         745 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	is_vid_mode = dpu_enc->disp_info.capabilities &
disp_info        1119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
disp_info        1610 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct msm_display_info *disp_info;
disp_info        1617 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	disp_info = &dpu_enc->disp_info;
disp_info        1629 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			   (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
disp_info        1843 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
disp_info        2038 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				 struct msm_display_info *disp_info)
disp_info        2061 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	switch (disp_info->intf_type) {
disp_info        2070 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	WARN_ON(disp_info->num_of_h_tiles < 1);
disp_info        2072 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
disp_info        2074 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
disp_info        2075 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	    (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
disp_info        2080 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
disp_info        2086 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		u32 controller_id = disp_info->h_tile_instance[i];
disp_info        2088 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		if (disp_info->num_of_h_tiles > 1) {
disp_info        2110 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
disp_info        2178 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		struct msm_display_info *disp_info)
disp_info        2189 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
disp_info        2197 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
disp_info        2211 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
disp_info         142 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 		struct msm_display_info *disp_info);