disp_dlg_regs 50 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); disp_dlg_regs 916 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->ref_freq_to_pix_freq = disp_dlg_regs 918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal disp_dlg_regs 920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits disp_dlg_regs 921 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end disp_dlg_regs 923 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start disp_dlg_regs 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); disp_dlg_regs 950 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->min_dst_y_next_start); disp_dlg_regs 1029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1401 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line disp_dlg_regs 1402 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk disp_dlg_regs 1403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs 1405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); disp_dlg_regs 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); disp_dlg_regs 1407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); disp_dlg_regs 1408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); disp_dlg_regs 1410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); disp_dlg_regs 1411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs 1413 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_vblank_l = disp_dlg_regs 1416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank disp_dlg_regs 1422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c disp_dlg_regs 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = disp_dlg_regs 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1431 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1436 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1440 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1442 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1451 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c disp_dlg_regs 1453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { disp_dlg_regs 1456 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_pte_row_nom_c, disp_dlg_regs 1461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1467 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1472 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1475 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1476 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1479 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_c = disp_dlg_regs 1483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = disp_dlg_regs 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, disp_dlg_regs 1497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, disp_dlg_regs 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1502 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, disp_dlg_regs 1504 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, disp_dlg_regs 1506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; disp_dlg_regs 1510 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_offset_cur0 = 0; disp_dlg_regs 1511 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; disp_dlg_regs 1512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_offset_cur1 = 0; disp_dlg_regs 1514 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; disp_dlg_regs 1515 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; disp_dlg_regs 1516 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; disp_dlg_regs 1517 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz, disp_dlg_regs 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); disp_dlg_regs 1524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off disp_dlg_regs 1560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c print__dlg_regs_st(mode_lib, *disp_dlg_regs); disp_dlg_regs 50 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); disp_dlg_regs 916 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->ref_freq_to_pix_freq = disp_dlg_regs 918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal disp_dlg_regs 920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits disp_dlg_regs 921 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end disp_dlg_regs 923 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start disp_dlg_regs 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); disp_dlg_regs 950 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->min_dst_y_next_start); disp_dlg_regs 1029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1401 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line disp_dlg_regs 1402 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk disp_dlg_regs 1403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs 1405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); disp_dlg_regs 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); disp_dlg_regs 1407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); disp_dlg_regs 1408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); disp_dlg_regs 1410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); disp_dlg_regs 1411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs 1413 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_vblank_l = disp_dlg_regs 1416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank disp_dlg_regs 1422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c disp_dlg_regs 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = disp_dlg_regs 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1431 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1436 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1440 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1442 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1451 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c disp_dlg_regs 1453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { disp_dlg_regs 1456 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_pte_row_nom_c, disp_dlg_regs 1461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1467 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1472 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1475 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1476 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1479 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_c = disp_dlg_regs 1483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = disp_dlg_regs 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, disp_dlg_regs 1497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, disp_dlg_regs 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1502 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, disp_dlg_regs 1504 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, disp_dlg_regs 1506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; disp_dlg_regs 1510 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_offset_cur0 = 0; disp_dlg_regs 1511 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; disp_dlg_regs 1512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_offset_cur1 = 0; disp_dlg_regs 1514 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; disp_dlg_regs 1515 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; disp_dlg_regs 1516 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; disp_dlg_regs 1517 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz, disp_dlg_regs 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); disp_dlg_regs 1524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off disp_dlg_regs 1560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c print__dlg_regs_st(mode_lib, *disp_dlg_regs); disp_dlg_regs 817 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 950 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); disp_dlg_regs 963 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->ref_freq_to_pix_freq = disp_dlg_regs 965 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal disp_dlg_regs 967 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits disp_dlg_regs 968 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end disp_dlg_regs 970 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 979 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); disp_dlg_regs 980 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); disp_dlg_regs 1001 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->min_dst_y_next_start); disp_dlg_regs 1069 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1071 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1076 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vready_after_vcount0 = 1; disp_dlg_regs 1078 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vready_after_vcount0 = 0; disp_dlg_regs 1474 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line disp_dlg_regs 1475 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk disp_dlg_regs 1476 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1477 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs 1478 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); disp_dlg_regs 1479 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); disp_dlg_regs 1480 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); disp_dlg_regs 1481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); disp_dlg_regs 1483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); disp_dlg_regs 1484 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs 1486 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); disp_dlg_regs 1487 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); disp_dlg_regs 1488 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); disp_dlg_regs 1489 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); disp_dlg_regs 1491 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_vblank_l = disp_dlg_regs 1494 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1497 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank disp_dlg_regs 1500 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c disp_dlg_regs 1504 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = disp_dlg_regs 1507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1509 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs 1510 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1512 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1514 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal disp_dlg_regs 1518 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip disp_dlg_regs 1524 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; disp_dlg_regs 1525 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; disp_dlg_regs 1526 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; disp_dlg_regs 1527 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; disp_dlg_regs 1530 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) disp_dlg_regs 1531 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; disp_dlg_regs 1533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) disp_dlg_regs 1534 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; disp_dlg_regs 1536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) disp_dlg_regs 1537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; disp_dlg_regs 1539 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) disp_dlg_regs 1540 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; disp_dlg_regs 1541 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1543 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); disp_dlg_regs 1546 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c disp_dlg_regs 1548 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { disp_dlg_regs 1552 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_pte_row_nom_c, disp_dlg_regs 1557 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); disp_dlg_regs 1561 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now disp_dlg_regs 1567 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1570 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1571 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1572 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1575 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1576 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1579 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_c = disp_dlg_regs 1583 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1584 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1587 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = disp_dlg_regs 1591 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1592 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1595 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( disp_dlg_regs 1597 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( disp_dlg_regs 1599 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1600 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1602 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( disp_dlg_regs 1604 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( disp_dlg_regs 1606 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1607 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); disp_dlg_regs 1609 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; disp_dlg_regs 1610 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_offset_cur0 = 0; disp_dlg_regs 1611 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; disp_dlg_regs 1612 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_offset_cur1 = 0; disp_dlg_regs 1614 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; disp_dlg_regs 1615 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; disp_dlg_regs 1616 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; disp_dlg_regs 1617 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil( disp_dlg_regs 1622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); disp_dlg_regs 1624 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off disp_dlg_regs 1660 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c print__dlg_regs_st(mode_lib, *disp_dlg_regs); disp_dlg_regs 981 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs, disp_dlg_regs 1116 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); disp_dlg_regs 1135 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->ref_freq_to_pix_freq = disp_dlg_regs 1137 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal disp_dlg_regs 1139 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end disp_dlg_regs 1141 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1142 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ disp_dlg_regs 1157 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start disp_dlg_regs 1159 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); disp_dlg_regs 1171 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->min_dst_y_next_start); disp_dlg_regs 1425 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */ disp_dlg_regs 1426 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */ disp_dlg_regs 1427 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1431 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_after_scaler); disp_dlg_regs 1435 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_x_after_scaler); disp_dlg_regs 1437 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); disp_dlg_regs 1441 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_prefetch); disp_dlg_regs 1448 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); disp_dlg_regs 1452 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); disp_dlg_regs 1506 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1; disp_dlg_regs 1508 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); disp_dlg_regs 1512 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1; disp_dlg_regs 1514 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); disp_dlg_regs 1516 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_vblank_l = disp_dlg_regs 1519 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1521 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_vblank_c = disp_dlg_regs 1524 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1526 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = disp_dlg_regs 1529 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1531 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs 1532 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ disp_dlg_regs 1545 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1547 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1549 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c disp_dlg_regs 1551 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1553 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1555 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); disp_dlg_regs 1557 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ disp_dlg_regs 1559 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l disp_dlg_regs 1562 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1563 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1565 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c disp_dlg_regs 1568 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1569 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; disp_dlg_regs 1571 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l disp_dlg_regs 1574 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) disp_dlg_regs 1575 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; disp_dlg_regs 1675 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( disp_dlg_regs 1678 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( disp_dlg_regs 1681 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1682 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1714 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( disp_dlg_regs 1717 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( disp_dlg_regs 1720 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1721 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); disp_dlg_regs 1723 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; disp_dlg_regs 1913 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c print__dlg_regs_st(mode_lib, *disp_dlg_regs);