disp0_lock        198 drivers/clk/mmp/clk-of-mmp2.c static DEFINE_SPINLOCK(disp0_lock);
disp0_lock        213 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
disp0_lock        218 drivers/clk/mmp/clk-of-mmp2.c 	{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
disp0_lock        219 drivers/clk/mmp/clk-of-mmp2.c 	{0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
disp0_lock        232 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
disp0_lock        233 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
disp0_lock        234 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
disp0_lock        182 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(disp0_lock);
disp0_lock        192 drivers/clk/mmp/clk-of-pxa168.c 	{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
disp0_lock        208 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
disp0_lock        188 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(disp0_lock);
disp0_lock        198 drivers/clk/mmp/clk-of-pxa910.c 	{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
disp0_lock        214 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},